AMD Launches 256-Core Zen 6 EPYC Venice CPUs for SP7

By Tom Whitfield

AMD launched its sixth-generation EPYC 9006 “Venice” server processors on Nov. 10, 2026, with the flagship EPYC 9996 combining 256 Zen 6c cores and 512 threads per socket. The chip uses TSMC’s 2nm-class N2P compute dies and the new SP7 socket.

What did AMD launch?

AMD unveiled the family in July and published list prices in September, ranging from $700 to $14,904, with the EPYC 9996 at the top. Its price roughly matched the launch price of AMD’s Turin flagship, while a smaller SP8 platform will follow early next year.

The EPYC 9996 raises the core count from 192 on last year’s Turin EPYC 9005. The frequency-optimized EPYC 9686F has 96 cores and boosts to 5.3 GHz, the highest clock in EPYC history according to ServeTheHome. Peak package power rises to 600 watts.

AMD also launched EPYC Embedded 9006 parts with up to 256 cores for chip-test equipment, storage arrays and network firewalls. AMD plans customer shipments for later that month. For buyers, Venice starts with a 256-core flagship and expands through smaller SP8 and embedded configurations.

Why does AMD invoke agentic AI?

AMD sells Venice as its best CPU for agentic AI, while Nvidia markets the 88-core Arm-based Vera for the same class of work. The case rests on a workload mechanism: an agent divides a task into steps that call tools, query databases and run code, much of which executes on CPUs.

AMD’s Madhu Rangarajan said agents drive CPU demand in search clusters, enterprise applications and databases. AMD claims the 256-core Venice chip at 400 watts handles 3.3 times as many concurrent agents per watt as Vera and 1.8 times as many agents per dollar as Intel’s Xeon 6. These are company figures rather than independent test results.

AMD nevertheless said it did not design Venice around agentic AI. Rangarajan told Tom’s Hardware: “We didn’t magically know four years ago that agentic was going to be a thing and purpose-built something for agentic.” Lead Zen architect Mike Clark said AMD had always believed the CPU would retain a role in AI software.

Nvidia calls Vera “purpose-built” for agentic AI, while Arm says its AGI CPU was designed for agents. AMD counters with Venice-X, which adds stacked cache for HPC, and the LPDDR5X-based Verano platform for Vera’s AI-host role, both due next year. The contest concerns workload efficiency, not exclusive suitability for agents.

What changed from Zen 5?

AMD claims an average 27% gain in instructions per clock over Zen 5 across enterprise, cloud and AI workloads. Tom’s Hardware said the figure came from a fixed-frequency comparison against the dense Zen 6c design.

The chiplet layout changes materially. A standard Zen 6 chiplet now holds up to 12 cores, up from eight, while dense Zen 6c holds 32, up from 16, and carries 128 MB of L3 cache.

A second I/O die gives each SP7 socket 16 memory channels, up from 12. It supports MRDIMMs at up to 12,800 MT/s for 1.6 TB/s of bandwidth per socket and up to 8 TB of memory.

PCIe advances to Gen 6, although Venice offers 96 lanes in a single-socket server against Turin’s 128 Gen 5 lanes. The wider platform favors core count, memory speed and newer I/O, but it trades PCIe lane count for scale.

How does Venice compare with Nvidia Vera?

Independent benchmarks appeared on launch day. Tom’s Hardware tested two-socket EPYC 9996 and 9686F systems against Turin, Intel’s Xeon 6980P and Nvidia’s 88-core Arm-based Vera reference platform. Its dual-9996 server scored 93% higher than a dual EPYC 9965 on SPEC CPU 2026 integer throughput.

Tom’s Hardware attributed that gain to faster cores and one-third more threads, while warning that it did not carry across every workload. The 96-core 9686F, described as AMD’s direct answer to Vera, led on most test suites: 17% on integer throughput, 40% on floating-point throughput, 32% on PyBench and 92% on Java SciMark.

Vera retained clear advantages in memory tests, C-Ray rendering and Octave. It also maintained ClickHouse performance from a cold cache while the x86 systems required a warm cache, giving the Arm processor an edge in memory-sensitive and cache-sensitive work.

StorageReview’s first full independent review of Vera measured two sockets sustaining 2,073 GB/s on STREAM Triad, which was 86% of the rating and 2.3 times the best DDR5 x86 server in its set. That comparison covered only previous-generation AMD and Intel chips, not Venice.

Vera also beat a 192-core EPYC 9965 socket by 26% on PostgreSQL in HammerDB. The 9965, however, led by about three times in GROMACS and AES across the full system, exposing Vera’s weakness in vector-heavy and encryption code. Venice leads most compute tests so far, but Vera still owns memory bandwidth and selected workloads.

What is the commercial outlook?

The Next Platform reported that AMD holds about 46% of the data-center CPU market. ServeTheHome said AMD expects Venice to push its x86 server CPU revenue share above 50% for the first time. That second figure is AMD’s expectation, not an independent forecast.

AMD enters the launch after a record quarter in which its data-center revenue nearly doubled. The competitive context also includes Oracle making Vera generally available on its cloud in October and Google adding two TPU systems in the launch week.

Pricing will test the claim: the $14,904 EPYC 9996 must convert early compute leads into deployments despite Vera’s bandwidth advantage and Intel’s Xeon 6 presence. With SP8, Venice-X and Verano due next year, AMD’s near-term objective is to turn higher core counts and claimed agent efficiency into the revenue-share gain it expects, a result the current benchmarks do not guarantee.