AMD's Venice-X hits 5.3 GHz and returns 3D V-Cache to servers

AMD's Venice-X will boost to 5.3 GHz, the highest clock in the EPYC family, and returns 3D V-Cache to the data center in the second half of 2027 after a four-year absence. The chip pairs 96 cores and 1,152 MB of stacked L3 cache with PCIe 6.0 and 1.6 TB/s of per-socket memory bandwidth, aiming squarely at HPC workloads.

The X-series has traveled a slow road. AMD introduced hybrid bonding on EPYC with Milan-X in 2022, followed with Genoa-X a little over a year later, and then skipped Turin-X entirely. Genoa-X, launched in 2023, was the last server part with stacked SRAM. Venice-X matches its core count and cache capacity but upgrades nearly everything around them.

What changes with the 5.3 GHz figure?

The story is frequency, not core count. Previous X chips capped well below their families' ceilings: Milan-X topped out at 3.5 GHz while standard Milan reached 4.1 GHz, and Genoa-X managed 3.7 GHz against Genoa's 4.4 GHz. Venice-X closes that gap by hitting the full 5.3 GHz boost available across the Venice range.

The likely SKU, an EPYC 9006X, matches the EPYC 9684X's 96 cores, 192 threads and 1,152 MB of L3 cache. AMD has not disclosed the base clock, the number of SKUs, or the TDP, though the 400 to 600 W range of other Venice CPUs is the plausible envelope. The part appears to use the SP7 socket, consistent with earlier EPYC-X chips.

How does the platform feed the chip?

Venice-X inherits the full SP7 feature set:

• 96 PCIe 6.0 lanes
• 16-channel memory support, including MRDIMMs at 12,800 MT/s
• 1.6 TB/s of quoted per-socket memory bandwidth

The smaller SP8 enterprise platform trades memory channels for PCIe lanes, but Venice-X takes the full 16-channel configuration. The combination of high clocks and bonded cache is, per AMD, precisely the marriage HPC customers want.

Why does AMD run its own workloads on it?

AMD uses both 3D V-Cache and high-frequency EPYC chips in its internal HPC fleet for EDA workloads. AMD Fellow Phil Steinke says the company runs performance analysis on these workloads to characterize performance, optimize EPYC designs, and push partners to optimize their software.

Function verification dominates that fleet, consuming over half of AMD's compute. These logic simulations appear in tools such as Cadence Xcelium, and Steinke says the EPYC team runs them "24 x 7 x 365." In one IPC measurement using AMD's uProf utility, a workload with 3D V-Cache completed 40 percent faster at roughly double the instructions per clock. AMD did not specify which chips or application it compared, only a fleet with and without the stacked cache.

Venice-X collapses that split into one part. "I mentioned we have a mix of high frequency and 3D V-Cache CPUs in our data center, and that's because through Milan and Genoa, the high frequency parts were always a little higher on the frequency side," Steinke said. "You don't have that dichotomy [with Venice-X]. You can get the best of both worlds in a single CPU."

What do the interim benchmarks show?

AMD has published no Venice-X benchmarks. It did share HPC results comparing the high-frequency EPYC 9686F against Intel's Xeon 6980P in workloads including computational fluid dynamics, where the 9686F ran 1.6x faster on 32 fewer cores. In Tom's Hardware testing, a 2P EPYC 9686F configuration finished the CloverLeaf hydrodynamics simulation in about a third of the time of a single Xeon 6980P, though the single-socket Intel result is sensitive to latency.

AMD will also keep using MEXT, its AI-driven flash-as-DRAM technology, to expand memory capacity for EDA workloads when Venice-X deploys.

The launch window matters as much as the silicon. Standard SP7 and SP8 Venice CPUs are rolling out now, while Venice-X and Verano, an AI host node built on SOCAMM2 LPDDR5X memory, both arrive in the second half of 2027, giving Intel a two-year window against uncontested stacked-cache parts.