AMD shares how it can retain 95% of server performance with just half the DRAM, sidestepping memory shortages with MEXT

Memory & Storage

AMD says MEXT keeps 95% of server speed on half the DRAM

AMD's MEXT offloads cold DRAM pages to flash with an AI predictor, claiming 95% performance at half the memory. It runs on 145 AMD servers today, 2,000 planned.

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Nathan Brooks
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AMD says it can retain 95% of server performance while running with just 50% of the physical DRAM, using a memory-offload technology called MEXT that is already deployed on 145 of its own servers. The company plans to expand that footprint to 2,000 servers next year. For data centers squeezed by record DRAM prices, the arithmetic is hard to ignore.

MEXT, a predictive memory engine AMD acquired in June, moves cold memory pages to flash storage and uses an AI model to fetch them back before the application asks. Founder Gary Smerdon says the technology can cut a server's physical DRAM requirement by 20% to 75%, depending on the application and performance target. The missing memory still appears to the operating system as installed DRAM. AMD has not published independent verification; these are first-party figures, and the benchmark slides carried footnote tags the company did not share.

How does the prediction work?

The core problem is simple. Flash is orders of magnitude slower than DRAM, so pulling pages back reactively would stall the workload. MEXT's answer is anticipation: a transformer-based LLM, similar in design to modern language models, predicts which memory page will be needed next. As long as the model stays ahead of the SSD's transfer latency, the DRAM behaves as if it was never absent.

The software ships as a Linux kernel module that runs on any distribution. It does not come pre-trained. AMD says it trains in under a second on first deployment, runs on a single EPYC core without a GPU, and continues learning access patterns as the workload progresses. Smerdon frames AI as the decisive difference from earlier flash-offload schemes. The model uses an "ensemble of AI models," with the transformer doing the primary work.

A companion tool, RAM View, visualizes which pages are hot and which have gone cold. In one AMD example, a system with 1.5 TB of memory showed near-full utilization while roughly half the pages sat untouched for five minutes or more. AMD did not name the workload in that example, and the breakdown varies sharply by application.

What do AMD's internal numbers show?

AMD shared results across three workload classes, all first-party:

  • Synopsys PrimeTime (EDA): 95% of full-server performance at 50% DRAM capacity, and 80% at 25% capacity.
  • Spark SQL on TPC-DS: a 3-node Azure cluster running 5th-gen EPYC CPUs delivered 99% of full-cluster performance at 50% DRAM capacity. Databases that cache aggressively in memory are a natural fit.
  • Agentic AI: across a five-agent concurrent geomean, AMD claims 99% performance at 50% capacity and 85% at 25%. A memory-hungry agent returned 90% and 88%, respectively.

AMD is also optimizing MEXT for database and media and entertainment workloads, beyond the EDA tools it runs internally.

When can customers buy it?

The rollout is deliberately staged. Phase 1 is underway: HPE is shipping "MEXT Ready" EPYC Venice servers with a dedicated NVMe drive or bay for the offload. Phase 2 adds the MEXT license and the RAM View application. AMD has not said when Phase 2 begins, nor when the technology will be available beyond its own infrastructure. MEXT is EPYC-exclusive for now, though AMD left the door open to consumer products such as Strix Halo far down the road.

The caution is telling. AMD says many workloads can safely shed 20% to 25% of capacity, but deeper cuts favor specialized applications with widening performance penalties. In a supply-constrained DRAM market, even the modest end of that range translates into serious savings. If the claims survive broad deployment, MEXT could become a defining technology for data centers that cannot get enough memory.

Source: Tom's Hardware

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Nathan Brooks

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Senior reporter covering people, launches and day-to-day practice in Semiconductors, chip manufacturing, hardware, AI compute at Chip Dispatch.

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