AMD Venice EPYC spans 31 SKUs, 256 cores and $14,904

By Sophie Lindqvist

AMD launches its sixth-generation EPYC “Venice” family with 31 announced SKUs spanning 8 to 256 cores, 130 to 600 watts, and per-chip prices of $700 to $14,904 in 1,000-unit trays.

SP7 models ship now. The 22 SP8 models remain on AMD’s roadmap for the first half of 2027. AMD says only that they “will ship sometime in the first half of 2027”; an early-2027 launch is an analyst estimate, not a company commitment.

AMD frames the growing design complexity as a response to a widening range of datacenter workloads. The family comprises nine SP7 and 22 SP8 SKUs, with two socket platforms, two I/O dies and two compute dies. The range leaves both configurations open to scrutiny. It does not prove that every part will reach volume production on the same schedule.

How do Zen 6 and Zen 6c differ?

Venice places Zen 6 and Zen 6c in one family, unlike the distinct families in Genoa and Turin. The cores retain the same cache hierarchy, but their schedulers use different optimizations: one favors higher core counts and lower clock speeds on compute dies, while the other favors fewer cores and higher clock speeds.

With Turin, AMD halved L3 cache on each Zen 5c compute die, or CCD. That allowed more cores on the die but reduced performance on cache-sensitive workloads.

AMD pairs the new cores with a 12-core CCD carrying 48 MB of L3 cache and a 32-core CCD carrying 128 MB. Both compute CCDs use TSMC’s 2 nm process, and either type can appear in either socket.

What do the two sockets change?

SP7 uses a pair of I/O dies and 16 DDR5 channels per socket. MRDIMMs at 12.8 GT/s provide up to 1.6 TB/s, while RDIMMs at 8 GT/s provide 1 TB/s. Each channel accepts one memory module, with capacity up to 512 GB.

SP7 also provides 96 PCIe 6.0 lanes at 64 Gb/s and eight PCIe 4.0 lanes at 16 Gb/s per socket. In a dual-socket system, 128 PCIe 6.0 and 16 PCIe 4.0 lanes remain external, while 64 PCIe 6.0 lanes provide the NUMA link.

AMD builds the SP7 I/O and memory die on TSMC 6 nm, the same node used for Turin but with a different design. Advanced nodes shrink compute more effectively than I/O, while the added process cost and signaling difficulty bring little benefit for this chiplet.

SP8 targets mainstream systems with two I/O dies and eight DDR5 channels, four per die, plus two DIMMs per channel interleaved for capacity. Its I/O die provides 128 PCIe 6.0 lanes and eight PCIe 4.0 lanes. AMD confirmed that the die uses TSMC 6 nm.

Relative to SP7, SP8 offers half the memory bandwidth but 33% more I/O lanes. In a two-socket NUMA configuration, 64 PCIe 6.0 lanes handle coherency and 192 remain exposed, alongside 16 PCIe 4.0 lanes.

What do the performance figures show?

The analysis calculates relative performance from core count, clock speed and generational gains in instructions per cycle, rather than measured benchmarks. On that basis, AMD claims a “20 percent” average per-core uplift for Zen 6 over Zen 5 at the same clock speed.

AMD made the EPYC 9G76 specifically for Helion AI racks. It resembles the HPC-oriented EPYC 9686F, but the analysis suggests AMD may discount them differently. Hyperscalers and cloud operators could obtain better terms because they buy in greater volume; no prices or contract data support that theory.

Against the November 2008 quad-core Shanghai Opteron 2393 SE baseline, the top-bin comparison covers standard EPYC parts from Naples onward and includes both Venice sockets. It excludes special HPC parts marked F for frequency optimization or X for extra vertical cache.

Shanghai was among AMD’s last competitive Opterons. It arrived as Intel’s Nehalem Xeon 5500 borrowed heavily from AMD’s work and gave Intel a competitive multicore design, while the Great Recession began and AMD struggled with Opteron. The model shows top-bin relative performance rising roughly linearly from Naples 7001 through SP8 Venice 9006; SP7’s 256-core part is the outlier.

Naples improved price/performance sharply, but nine years separated it from Shanghai and Moore’s Law still supplied gains. Shanghai used TSMC 45 nm; Naples used GlobalFoundries 14 nm.

Rome then drove price/performance aggressively after AMD introduced compute chiplets linked by an I/O die. Milan’s top-bin performance rose while value gains slowed; Genoa repeated that pattern.

Turin and Venice push the price/performance envelope again, especially through SP7. SP8 carries a modest premium despite roughly half as many cores and somewhat higher clocks, because added clock speed raises heat faster than added cores after process shrinks.

For EPYC 9996 SP7, the model calculates 190 times the performance of Opteron 2393 SE, with cost per unit of performance 14.9 times lower. The processor itself costs 12.8 times more. The analysis links that premium to server consolidation, agentic AI and traditional HPC.

For EPYC 9746 SP8, it calculates 108.2 times the baseline performance, 10.8 times better value per dollar, and a 10-fold chip price. Middle-bin results follow a flatter curve but still show stronger Venice value than earlier EPYC generations.

The assessment says AMD has gained server share with each recent quarter, but it provides no quarterly figures. It also places hyperscalers and cloud builders at roughly half of the server market and says Arm-based processors are rising among them. Intel remains the stated x86 rival. Those claims frame the competitive pressure, but no Arm shipment, market-share or benchmark data appears.

What remains unproven?

The SP8 schedule remains a roadmap; SP7 is the shipping platform. The performance and value comparisons are modeled estimates, not independent tests, and the Helion discount theory is speculative. The announcement and comparison give no wafer diameters, fab capacity, revenue forecast or customer commitments.

Those omissions limit any conclusion about manufacturing scale, pricing durability or share gains. Venice’s clearest launch advantage is architectural breadth—2 nm compute dies across two sockets—but the commercial test comes when SP8 systems ship in 2027.

The next proof points are SP8 shipments in 2027, realized pricing, and whether the modeled value gains translate into share against Intel and Arm.