Analog Devices Engineers Show Why 90 dB Demands a Two-Stage Filter

A two-stage LC input filter delivering more than –100 dB of attenuation at 1 MHz — built from a 1-µH inductor — beat a single-stage design that needed a bulky 33-µH part and barely scraped its –90-dB target. That comparison anchors a new Analog Devices application note by field applications engineer Rani Feldman, which walks designers through building and simulating differential-mode input filters for switching DC-DC regulators in LTspice.

The premise is simple. Switching regulators convert power efficiently, but their pulsed input current carries rich harmonic content that propagates back onto the power bus and disturbs sensitive analog, RF, and communication circuits. An input filter is the first line of defense. Treat it as a bolt-on afterthought, though, and its resonance, damping, impedance interaction with the converter, and startup behavior can all wreck the system.

What does capacitor ESR actually do?

An LC filter is a double-pole network: –40 dB/decade of attenuation below the capacitor's ESR zero. Feldman's baseline example fixes the resonant frequency f0 at 33.4 kHz and steps the capacitor ESR between 1 mΩ and 100 mΩ. The zero shifts from 7.23 MHz down to 72.34 kHz — and at a 1-MHz switching frequency, the attenuation difference reaches 22.7 dB. The ESR zero flattens the slope from –40 dB/decade to –20 dB/decade and caps achievable high-frequency attenuation.

Low ESR cuts both ways. Because an LC filter is a resonant RLC network, very low ESR produces high Q and significant peaking at f0. The filter's output impedance spikes. Per the Middlebrook criterion, that output impedance must stay below the converter's input impedance or the system destabilizes.

The fix is a series RC damping branch in parallel with the filter capacitor, sized for Q ≈ 1. Feldman's worked example uses a 1-mΩ-ESR capacitor, a damping capacitor at 4.5× the filter capacitor, and a calculated 0.213-Ω damping resistor, rounded to 0.2 Ω. The result: no peaking, with –58 dB of attenuation at 1 MHz. Damping capacitors typically run 3× to 10× the filter capacitor value.

Inductor selection carries its own tradeoffs. High inductance slows load-transient response; high DCR wastes voltage drop and power in the series path. Cut the inductance for a given f0, and capacitance must rise to compensate.

What breaks without damping?

Feldman names two failure modes. First, startup overvoltage: the input can ring to nearly twice VIN. A 12-V-to-5-V design with a 42-V absolute maximum rating survives; a 28-V-to-5-V design can exceed it and destroy the IC.

Second, output oscillation. Using the built-in LTspice schematic for the LT8609S with an added undamped filter — where f0 is set by L2 and the total capacitance CT = C7 + C8 + C9 — the simulation shows the output oscillating at the filter's resonant frequency. Probing the after_filter net exposes the cause: the input voltage itself is ringing, peaking at 46.6 V. That clears the LT8609's 42-V absolute maximum input rating.

How much attenuation does MIL-STD-461G require?

The flagship design example converts 15 V to 5 V at 3 A for a radio receiver, switching at 1 MHz, and must pass MIL-STD-461G. Feldman selected the LT8624S, a Silent Switcher 3 device, for its low noise and low EMI, and derived component values from the datasheet and LTpowerCAD.

The standard sets conducted-emission limits for power leads in CE101 from 30 Hz to 10 kHz and CE102 from 10 kHz to 10 MHz, measured in dBµV through a LISN. The LISN presents roughly 50 Ω of known impedance and converts the equipment's conducted current into a measurable voltage. For systems below 28 V, the CE102 basic curve holds a flat limit near 60 dBµV above about 1 MHz — equivalent to 1 mV.

The LTspice workflow: plot I(V1) by hovering the cursor over the voltage source, run View → FFT in the waveform viewer, then switch the left axis from decibel to linear. The simulated input current magnitude lands at about 657 mA. Multiply by the 50-Ω LISN impedance — 32.85 V — and convert to dBµV, and the required filter attenuation works out to 150 dB – 60 dB = 90 dB. Equivalently: 657 mA divided by the 20-µA allowance gives 32,800, and 20·log(32800) = 90.31 dB.

Why one stage wasn't enough

Hitting 90 dB with a single LC filter pushes components past practical limits. A 4.7-µH inductor chosen first forces a capacitor so large that damping alone would need at least 3 × 170 µF = 510 µF. Raising the inductor instead cuts component count but bloats size, cost, and transient response.

The two-stage solution forms a fourth-order filter with an –80 dB/decade slope before the ESR zero, letting f0 sit 10× higher for the same target. In the comparison, f0 = 56.2 kHz; the single-stage filter needs 33 µH, the two-stage only 1 µH. Simulations show the single stage barely reaching –90 dB — and only with capacitor ESR of 2 mΩ or less, meaning the ESR zero is already eroding its slope. The 33-µH inductor is too large for 1-MHz switching and ill-suited to fast transients.

The two-stage filter exceeds –100 dB with smaller parts, and that margin matters: it keeps the 90-dB target within reach even after capacitors derate under bias voltage and temperature.

Feldman, who joined Analog Devices in 2017 after three years at Linear Technology, closes with practical guidance: start from the emissions target, choose the smallest inductance that meets it, add intentional damping, check for peaking and startup overshoot, and validate in both frequency and time domains before LISN bench measurements. The through-line for power designers is clear — an input filter must be engineered simultaneously as an EMI filter and as a stable power interface, or it will fail as both.