ASML has secured backing from Intel, TSMC and Samsung for a move to 12-inch photomasks — and among the three leading-edge customers, only TSMC has so far put a timeline on adoption, according to DigiTimes.

The shift matters because masks are the master templates from which every lithography exposure is made. Today's high-volume advanced-node production runs almost entirely on 6-inch (150 mm) mask blanks, a format that has served the industry from the era of contact printing through extreme ultraviolet lithography at 3 nm-class nodes. Doubling the reticle format to 12 inches would, in principle, roughly quadruple the printable die area per mask — a direct answer to the steady shrink in usable wafer real estate economics as chipmakers stitch ever-larger dies for AI accelerators and advanced packaging.

For ASML, the initiative fits a familiar pattern. The Veldhoven-based equipment maker has historically driven pre-competitive infrastructure changes through its customer ecosystem — the Customer Support Center model, EUV source development with Cymer, and High-NA EUV rollout with Intel as launch partner all followed the same playbook. Getting Intel, TSMC and Samsung to align behind a common mask format repeats that approach: no single chipmaker can justify the cost of a new mask infrastructure alone, but a shared roadmap spreads the burden across the three companies that buy the overwhelming majority of ASML's most advanced scanners.

The commercial stakes sit with the mask supply chain as much as with the chipmakers. Mask blank production, e-beam writing tools and inspection equipment are all built around the 6-inch standard today. A transition to 12-inch blanks would force write-offs and re-investment across photomask makers such as Toppan, Dai Nippon Printing and Photronics, and across the suppliers of pattern-generation and inspection tools — unless the installed base is given a long enough runway. That is precisely why the absence of firm timelines from Intel and Samsung, with only TSMC committing to a schedule so far, leaves the actual transition economics unresolved.

TSMC setting a timeline first is consistent with its position as the largest buyer of EUV scanners and the foundry carrying the heaviest exposure to high-end mask counts. AI and HPC customers at N5, N3 and the coming N2 and A16 nodes consume reticles at a rate that makes mask cost per wafer a material line item. A larger mask format that prints more die per exposure could cut per-die mask amortization and reduce overlay steps on very large designs.

Still, a commitment from three chipmakers to a format direction is a roadmap, not a fab order. DigiTimes' report does not specify a target node, a mask blank supplier transition plan, or a first production date beyond TSMC's stated schedule. The open questions are the ones that will decide whether 12-inch masks become real capacity or stay a paper standard: which scanner generation supports the larger reticle stage, how mask blank suppliers retool, and whether the format arrives before high-NA EUV and subsequent tool generations lock in their own stage designs.

The industry will be watching TSMC's timeline as the anchor: if its schedule holds and blank suppliers commit retooling budgets against it, Intel and Samsung's stated support is likely to convert into firm infrastructure investment across the mask supply chain.