China's all-CPU "LineShine" supercomputer scored just under 2.2 exaflops on the High Performance Linpack benchmark, claiming the June Top500 number one ranking and surpassing Lawrence Livermore National Laboratory's "El Capitan" by 21.5 percent.

The system runs at the National Supercomputing Center (NSC) Shenzhen, according to an April 17 paper titled "Breaking the Training Barrier of Billion-Parameter Universal Machine Learning Interatomic Potentials" and a follow-up presentation by LineShine architect Yutong Lu at the HACI 2026 forum held May 22 to 25 in Shenzhen. Slides from Lu's talk were later posted by Torsten Hoefler of CSCS and Tadashi Ogawa of Panasas.

What CPU sits at the heart of LineShine?

LineShine uses the LingKun LX2 processor, a custom Armv9.2 design with SVE2 vector units and SME matrix blocks, co-developed by NSC Shenzhen and Huawei's HiSilicon chip division.

Each LX2 socket exposes 304 active cores drawn from 384 raw cores across two chiplets. That 79.2 percent yield rate strongly suggests manufacture at SMIC, probably on the foundry's 7-nanometer N+3 process, given China's limited access to leading-edge lithography.

The chip runs at 1.55 GHz, well below the 3 GHz SMIC can reach on that node, and burns 690 watts per socket. NSC Shenzhen deliberately slowed clocks to balance memory bandwidth against core throughput.

The slow clock carries a measurable tradeoff: LineShine consumes 42.2 megawatts in its benchmark configuration, well above the sub-30-megawatt draw reported for Frontier, El Capitan, and Aurora in the United States. That gap is significant but expected for a CPU-only design at a trailing-edge node.

How is memory organized?

Each LX2 socket carries 64 GB of HBM arranged in eight stacks per chiplet (16 stacks per socket) at roughly 8 TB/sec aggregate bandwidth, plus 256 GB of LPDDR5X DRAM organized into eight NUMA domains. The DRAM tiles stack on the compute package through 3D stacking with custom logic wafers, likely supplied by ChangXin Memory Technologies.

The April paper reports the LX2 supports FP64, FP32, FP16, and INT8 through its SME and SVE2 units, delivering up to 60.3 teraflops at FP64 precision and 120.6 teraflops at FP32 precision per socket. The paper does not separate SME from SVE2 figures, nor does it disclose FP16 or INT8 throughput, leaving a gap that independent benchmarking would have to close.

What configuration ran the HPL benchmark?

The benchmarked LineShine deployment runs 13,789,440 cores across 22,680 LX2 nodes in 184 frames, hitting a peak theoretical performance of 2.74 exaflops at FP64 precision.

The standard production configuration described in the April paper calls for 20,480 nodes and 12,451,840 cores, a footprint well below what the benchmarked deployment required for its headline number. China can scale the system further if required; the published material does not specify a ceiling.

Computational efficiency on HPL reached 80.35 percent. That trails the Fujitsu-built K computer's 93 percent record, the high-water mark on this benchmark. Fugaku, also by Fujitsu, posts 82.3 percent on the same test.

How does the interconnect scale out?

Nodes link through a proprietary "LingQi" fabric implemented as a four-layer fat-tree topology in dual-plane, multi-rail configuration. Per-node bandwidth reaches 1.6 Tb/sec across two 400 Gb/sec ports, with the entire fabric built on copper for internal links and optics only at the highest aggregation tier.

Single-hop latency measures 1.07 microseconds, a figure the published analysis describes as resembling Ethernet more than InfiniBand. Each node pairs two LX2 sockets. Eight nodes populate a blade. Sixteen blades form a frame rated at 30.87 petaflops at FP64 precision.

What does this mean for compute economics?

LineShine delivers 46.7 percent more HPL performance than its predecessor OceanLight on 32.9 percent fewer cores, a generational leap driven by SVE2 and SME additions plus chiplet-based scaling. The system runs entirely on indigenous compute engines and Chinese foundry capacity.

US export controls on Nvidia and AMD accelerators continue to push China toward self-designed CPU-GPU hybrids built on domestic process nodes rather than waiting for political winds to shift. No GPU software stack means no CUDA tax; that gain, however, is offset by higher power draw and lower per-core clocks. Nothing comes free in HPC software stacks, the published analysis concludes.

What could come next?

LineShine's all-CPU architecture with merged HBM and DRAM could reshape inference economics for agentic AI workloads. The LX2 belongs to a small group of CPUs, alongside IBM Power 10 and Power 11 and Intel Xeon 6 P-core, positioned for that workload mix.

Whether LineShine's full 20,480-node configuration enters steady production service remains undisclosed in the published material reviewed, leaving a gap between benchmark ceremony and operational reality. The November Top500 list will show whether LineShine holds its slot or yields to upgrades at Lawrence Livermore or Oak Ridge.