NextSilicon has spent eight years and $303 million across seed and three venture rounds delivering its 64-bit dataflow engine, Maverick-2, manufactured on TSMC's 5nm process with 54 billion transistors. The chip targets high-performance computing, with Sandia National Laboratories expected to take the first production deployment.

How does Maverick-2 differ from a GPU?

NextSilicon co-founder and vice president of architecture Ilan Tayari, formerly director of software at Mellanox, framed the design as a reaction to decades of accumulated overhead in classical processors. "Today's high end processors have become complicated and chunky," Tayari said at the launch event. "They dedicate 98 percent of their silicon to overhead, traffic management, data shuffling — not actual computation — and add more complexity."

The company labels the approach Intelligent Computing Architecture (ICA). Instead of a unified memory space and a single instruction fetch unit, Maverick-2 arranges hundreds of arithmetic logic units (ALUs) per compute block and maps instructions directly onto them. C, C++, or Fortran source compiles to a graph called a mill core, which lays down on the ALUs and reconfigures on a nanosecond timescale as workloads shift.

What does the die contain?

Maverick-2 carries roughly 54 billion transistors on TSMC's 5nm node. The die places 32 RISC-V E-cores on the left and right edges and arranges 224 compute blocks in a seven-column by thirty-two-row grid at hundreds of ALUs each. The arithmetic units run at 1.5 GHz, on par with a slow CPU or a mainstream GPU, and connect to HBM3E memory for bandwidth.

Power budgets climbed from last year's roadmap. A single-die Maverick-2 now draws 400 watts, up from 300 watts, while the dual-chip OAM module reaches 750 watts, up from 600 watts. NextSilicon does not disclose how many floating-point units sit inside each compute block.

What does the software do?

The compiler partitions an application between the host CPU (still an unnamed x86 part), the 32 embedded RISC-V cores, and the dataflow blocks. Roughly the eighty percent of runtime that benefits from parallel execution moves to the ALUs; serial code stays on the host. The compiler also monitors how the resulting dataflow behaves and reshapes the mill cores continuously, so applications tune themselves the longer they run. There is no CUDA-X or ROCm porting step.

What is Arbel, and why build a CPU?

NextSilicon disclosed Arbel, a "test chip" RISC-V processor intended to pair with Maverick-2 and remove the dependency on third-party x86 or Arm hosts. The Arbel core issues ten instructions wide, carries six integer ALUs and four 128-bit floating-point units, supports sixteen scalar instructions in parallel, and includes 64KB of L1 instruction cache, 64KB of L1 data cache, and 1MB of L2. NextSilicon claims the design can "stand toe-to-toe" with Intel's LionCove Xeon core and AMD's Zen 5 Epyc core, though core counts and packaging remain undisclosed.

Do the benchmark numbers hold up?

The published figures invite skepticism. A single Maverick-2 lands at roughly one third of Nvidia H100 peak FP64 performance, which sits at 33.5 teraflops on vector units and 67 teraflops on tensor units.

On GUPS, Maverick-2 reached 32.6 GUPS at 460 watts — claimed as twenty-two times faster than a CPU and nearly six times faster than a GPU, though neither rival was named. The OAM module posted 5.2 TB/sec on STREAM, or 83.9 percent of theoretical peak, at 1.86 times the performance per watt of an unspecified GPU.

HPCG measured 600 gigaflops at what appears to be dual-chip power, and PageRank ran ten times faster than "leading GPUs."

Until NextSilicon publishes the counterpart part numbers, the numbers belong in the interesting-but-unverified column rather than a procurement spreadsheet.

What comes next?

Expect fuller benchmark disclosures and an answer on scale-out networking before any HPC center signs a multi-rack order. Maverick-2 moves from paper to production today; whether sustained performance survives independent testing is the question that decides whether the $303 million ends as a footnote or a category.