IndexBox has published a semiconductor chemical vapor deposition (CVD) equipment market forecast extending to 2035 — a ten-year horizon — and named gate-all-around (GAA) transistor adoption and 3D NAND layer-count scaling as the two structural drivers behind expected tool-order growth.

The research firm stretches its lens well past the three- to five-year capital-equipment cycle that most fab-tool analysts track. CVD — gas-phase thin-film deposition run inside vacuum chambers between roughly 400°C and 800°C — anchors both front-end transistor builds and back-end memory stacks.

GAA swaps the fin-shaped tri-gate geometry used at 5nm and 4nm for horizontal nanosheet stacks wrapped fully by the gate electrode. Samsung Foundry moved 3nm GAE (gate-all-around early) into volume production in mid-2022, the first foundry to ship a GAA logic node. TSMC has stated its N2 node, targeted for 2025, will be its first GAA generation, with Intel's 18A process following on a similar timeline. The architecture deposits alternating layers of silicon and silicon-germanium, then etches away the SiGe to leave free-standing Si channels. That structural shift multiplies deposition steps per device, particularly for work-function metals such as TiN and TaN, the high-k HfO2-based gate dielectrics and the low-k SiOCN spacers that isolate each nanosheet. Every new GAA step adds ALD and CVD cycles per wafer, lifting the tool count required per fab ramp at a time when leading-edge fabs already run 1,500 process steps per wafer pass.

3D NAND has climbed from 64-layer devices in 2017 through 176-layer and 232-layer production parts at Samsung, SK hynix and Micron, with SK hynix publicly disclosing a 321-layer roadmap in 2023 and Samsung targeting 300-layer-plus stacks in the late 2020s. Each added tier in the vertical stack adds deposition steps for the alternating oxide-nitride (ONO) dielectric and the polysilicon channels. Memory holes more than ten microns deep demand conformal CVD films that coat sidewalls uniformly — a problem that has historically favored batch furnace and high-aspect-ratio single-wafer ALD tools.

What does the IndexBox forecast assume?

The study assumes foundry capex keeps expanding through 2035 to absorb AI accelerator demand, and that memory makers hold the layer-count cadence rather than pivoting to alternative cell architectures such as CBA (CMOS-bonded-array). If GAA adoption slows — say, if cost pressures push foundries to extend FinFET nodes past 3nm — or if 3D NAND plateaus around 400 layers, deposition equipment demand could flatten well before 2035.

Applied Materials, Lam Research, Tokyo Electron and ASM International collectively supply most of the world's CVD and ALD tools by revenue, according to industry tracking data. Specialized vendors including Aixtron in MOCVD and Veeco Instruments in compound-semiconductor deposition hold narrower positions. Detailed unit-volume assumptions, regional breakdowns and segmentation tables in the IndexBox report sit behind a paid subscription; methodology details have not been disclosed in publicly available excerpts.

The report joins a crowded field of deposition-equipment forecasts as the industry digests record 2024 fab-tool spending and watches the 2nm GAA ramp take shape across Samsung, TSMC and Intel. Whether deposition tool demand tracks the firm's 2035 trajectory depends on AI accelerator volumes, HBM3E and HBM4 bit-growth, and the cell-architecture choices memory makers make in the second half of the decade.