CXMT plans to ship its first 4F² DRAM product, a server DDR5 RDIMM, by the end of this year. Company president Cao Kanyu announced the timetable at the Integrated Chips and Chiplets Conference on Saturday, in remarks reported by Yicai. The date is firm in his statement. The product details are not.

The memory will use a denser cell layout based on vertical transistors. On paper, the design cuts each memory cell's footprint by roughly one third. CXMT has disclosed no speeds, no capacities, no process node and no named customers for the new RDIMM. The company has not published a release on the product in its Chinese or English newsrooms.

The claim matters because no vendor has commercialized a 4F² cell. Samsung and SK hynix have shown the design only in research papers. If CXMT ships first, it would move ahead of the two largest DRAM makers on a technology both have pursued for years.

What is a 4F² cell?

A 4F² cell measures 2F by 2F. At the same feature size, it occupies about two-thirds the area of the 6F² cells used in current DRAM production. All published 4F² designs stand the transistor on its end.

Cao said CXMT's version, called the Vertical Surrounded Gate (VSG) transistor, has a channel that stands vertically with the gate wrapped around it, allowing stronger gate control with less leakage. Most importantly, standing the transistor up shrinks the cell. He said CXMT now holds more than 300 published patent families tied to 4F².

The company's supporting record is real. CXMT has published research and patent filings on the technology with papers in 2021, 2023 and 2025. It demonstrated an 8Gb full-array research example at IEDM 2023.

Cao also described CXMT's work on wafer-level hybrid bonding, which began in 2019 and has produced published patents. The report notes the industry is moving toward 4F² combined with 3D solutions that decouple DRAM and CMOS processes, so logic and cell density can be optimized independently.

Where do Samsung, SK hynix and Micron stand?

Samsung presented a 16Gb, 10nm-class 4F² DRAM design in its ISSCC 2026 paper in February. That design also used vertical-channel transistors, with the array bonded on top of the periphery using wafer-to-wafer hybrid copper bonding. Samsung claims the bonding raises dies per wafer by more than 20% at the same design rules.

In April, The Elec reported Samsung had a working 4F² vertical-channel-transistor die on its sub-10nm "10a" process, with mass production targeted for 2028. Later South Korean reports muddied that timeline. Samsung has split the VCT version off as "D0a-V" with no stated schedule, and there is no firm date for adopting 4F².

SK hynix laid out plans at VLSI 2025 for a 4F² vertical-gate platform and 3D DRAM at nodes of 10nm and below, with circuitry bonded under the cell array. The April report also placed SK hynix's 4F² debut at the 10b node, one step after Samsung's 10a. Micron's plans remain unclear, with no widely reported 2026 statement.

How strong is CXMT's position in DRAM?

CXMT is China's primary DRAM maker and has gained share quickly. Its fifth-generation G5 DRAM technology platform, announced Sept. 20, is in mass production. TrendForce puts CXMT's share of global DRAM revenue at 9.5% in the second quarter, up from 7.6% in the first quarter. That is good for fourth place among DRAM makers.

Last November, CXMT demonstrated DDR5-8000 and LPDDR5X-10667 products. The company has established itself as a manufacturer the largest incumbents must take seriously.

What was left unsaid?

The announcement is more notable for its omissions than its details. CXMT disclosed no capacity, no speed, no die density, no process node, no named customers and no intended volume. Beyond Cao's talk, the company has released nothing that outside parties have tested.

South Korean reports have said CXMT's initial products may only partly use 4F², and that producing stable units at volume is a separate challenge from demonstrating a working cell. With roughly 11 weeks left in the year, the industry will judge the claim on what CXMT actually delivers — and on whether a fourth-place DRAM maker can commercialize a cell architecture the market leaders have so far kept in the laboratory.