Micron Axes 4F2 DRAM, Bets on 400-Layer NAND and High-NA EUV

Micron has cancelled plans for 4F2 DRAM cells and will mass-produce its 1-delta node in the second half of 2027, the company disclosed at its technology event last month. The roadmap through 2030 covers High-NA EUV lithography, wafer bonding, 3D DRAM, 400-layer NAND, and a return of custom memory to volume production.

"DRAM is nearing atomic limits at this point: although we have confidence in several more planar nodes, we are very focused on making sure that we introduce 3D DRAM at the optimal time from a cost and performance point of view," said Scott DeBoer, Micron's president and chief technology and products officer.

Why did Micron drop 4F2 cells?

Unlike CXMT, Samsung, and SK hynix, Micron sees no viable scaling path beyond its current 6F2 cell design. Its 1-gamma node, already in high-volume manufacturing, is Micron's first DRAM process to use EUV lithography after years of DUV multipatterning kept it competitive.

The 1-delta node is in yield ramp today and targets mass production in the second half of 2027, built in the United States. Micron expects mid-20% bit density gains over 1-gamma, plus improvements from high-k metal gate CMOS, new materials, angstrom-level process control, and equipment intelligence. The node will serve DDR, LPDDR, graphics memory, HBM5, vertical HBM, and vertical Edge Inference Memory, with through-silicon vias for thermal performance.

The successor 1-epsilon node will adopt wafer bonding, letting Micron build structures on separate wafers and join them, though it has disclosed no schedule, no density target, and no bonded structures. Zeta-angstrom, in early development, brings High-NA EUV into memory production but will not arrive before 2030, roughly two years after Samsung and SK hynix plan High-NA insertion at their DRAM fabs in 2028. Eta-angstrom sits in pathfinding and will lean on unidentified new materials. Micron offered a firm production window only for 1-delta.

Two 3D DRAM generations, called 3D1 and 3D2, are in parallel development; Micron disclosed no architectures, layer counts, or density targets, and will introduce the technology only when costs and performance match planar DRAM.

What does custom memory look like?

Custom memory becomes mainstream, starting with custom HBM4E. Customers can shrink memory I/O width or add logic to the base die, freeing accelerator die space for compute.

"When we co-design a base die, the certain logic elements that are desired to be put in that base die are generally an offload from GPU circuitry anyway onto the base die to put it closer to the memory," DeBoer said. "Moving what makes more sense onto the base die will still be a reality in [the] vertical HBM timeframe as well."

Micron will use advanced foundry processes for base dies and expects HBM4E to require more advanced CMOS to hit performance and power targets. Vertical HBM stacks memory directly on ASICs and CPUs rather than beside them on an interposer, promising higher bandwidth and lower latency but demanding hybrid bonding, integrated heat spreaders, and thermally aware designs for power delivery and heat dissipation. Conventional HBM and vHBM will coexist in some designs, vHBM for bandwidth, standard HBM for capacity.

First-generation vEIM targets HBM4-like bandwidth of 2 TB/s at under 1 picojoule per bit, aimed at power-sensitive inference rather than peak bandwidth. Micron is also working with Meta to tune LPDDR6 for data center reliability, expecting about 35% lower power than LPDDR5, and will develop DDR6, targeting double DDR5 bandwidth, with major customers.

"Across our AI co-invention opportunities we are co-imagining, co-designing, co-developing, co-validating, and then delivering at scale," DeBoer said. "This opportunity is truly unique. It is very different than the way we interacted with customers even three or four years ago."

How far can NAND scale?

Eleventh-generation 3D NAND, codenamed N170, raises active layers from 276 on G9 to more than 400, adds wafer-on-wafer bonding, and doubles bit density, from a presumed 21 Gb/mm2 to 42 Gb/mm2 for TLC. I/O speed rises 50%, implying about 5,400 MT/s, and transfer energy per bit drops more than 25%. Mass production is set for the second half of 2027.

YMTC pioneered wafer-on-wafer bonding, and Micron's adoption follows the same logic: build the array on one wafer, periphery and I/O on another, then bond. Beyond G11, Micron cites high-mobility materials, ultra-dense cell architectures, and continued XYZ scaling, without naming materials or quantitative targets.

"Beyond G11, we have a strong roadmap, not going to go into great detail on it today, but really focused on new materials densifying the cell architecture, and continuing to focus on that XYZ scaling going forward," DeBoer said.

What about AI-specific NAND?

Two specialized NAND families are in development. High-IOPS AI NAND uses SLC designs with small blocks for vector searches, graph analytics, and AI context management, targeting 25 million to 100 million IOPS with products expected within a couple of years. High-Bandwidth AI NAND stacks NAND vertically through TSVs with a logic base die near compute.

"[The High-Bandwidth AI NAND is] more costly and has to be implemented in partnership with customers in a way to ensure that they are meeting the mark and the cost point to drive the value proposition," DeBoer said. "We do not think placing it along the shoreline of the GPU has merit. Instead, we want to position it closer to the compute itself."

Micron's CMOS logic roadmap, spanning HKMG generations and two 3D CMOS generations, targets more than 10X performance gains between 2020 and 2030, while its SSD roadmap extends to 512 TB drives. The disclosed schedule leaves 1-delta and G11, both landing in late 2027, as the only committed production dates, meaning competitive pressure from Samsung and SK hynix High-NA insertion in 2028 will test whether Micron's 6F2-plus-bonding strategy holds cost parity.