d-Matrix expects to tape out its Raptor XPU before the end of 2026, the company said on September 11, partnering with Nvidia on a multi-year roadmap that places the decode-phase processor inside Nvidia's AI factory stack.

What is Raptor, and why does the memory matter?

Raptor pairs a compute die face-to-face with a custom DRAM die through microbumps, a configuration the company calls 3D digital in-memory compute (3DIMC). The architecture eliminates the conventional PHY, interposer, and long-distance data movement used by HBM. The trade-off is an SRAM pool that scales until it falls short of the largest reasoning models, where token counts outrun on-chip memory.

The bandwidth claim is the headline number. d-Matrix puts the per-stack figure at 20 TB/s, against roughly 2 TB/s for HBM4, and a power draw of 0.3–0.4 pJ/bit against HBM4's 3–4 pJ/bit. The mechanism is direct bank-to-compute access at a few hundred megahertz on the DRAM base, treating the DRAM die as an active partner rather than a passive capacitor.

"We took passive DRAM we use for capacitors and converted that to an active stack," d-Matrix said. "By doing that we can expose every small bank in the DRAM and directly bring it to the compute engine."

The design is built for NVLink Fusion and the Nvidia MGX rack-scale ecosystem. d-Matrix says more than 100 patents cover the approach, and that hyperscalers and frontier labs are already evaluating it.

The takeaway: if Raptor tapes out on schedule and the bandwidth numbers hold in silicon, the memory bottleneck conversation moves from HBM roadmaps back to the die-to-die interconnect.

Is China closing the HBM gap?

The Information reports that CXMT has begun small-volume production of HBM3E and intends to scale through 2027. HBM3E is the generation now shipping into Nvidia Blackwell systems from SK Hynix and Micron, making any domestic Chinese production a commercial signal as well as a technical one.

CXMT has not disclosed die density or stack height for its HBM3E. The Information's framing is small quantities rather than volume production, which leaves 2027 as the year that would test whether Chinese AI accelerators can pair with a domestic HBM supply.

The takeaway: HBM3E samples in 2026 are a milestone; HBM3E volume in 2027 is the test.

How long does the memory cycle last?

SK Hynix chief executive Kwak Noh-Jung said there are no clear signs of a memory downturn, and that the situation will continue through the end of 2030. "Even if a downturn comes, it will be closer to a gradual decline or flat trend rather than a steep drop," Kwak said. "After 2030, I believe supply and demand will find balance and the entire AI industry can grow together."

The statement matters because SK Hynix is the dominant HBM3E supplier today. A four-year visibility window from the largest vendor shapes pricing assumptions across the DRAM stack, from DDR5 to HBM4 and beyond.

The takeaway: the leading HBM maker is telling customers to plan for tight supply through at least 2030.

What is Micron paying its Taiwan workforce?

Reuters reports that Micron is offering Taiwan employees payouts of 35 to 68 months of salary for fiscal 2026, with a minimum cash floor of NT$1.7 million, about US$53,809. Local unions said 80 percent of Micron's Taiwan workers supported a strike, citing a gap between the bonus structure and the company's record AI-fueled revenues.

Samsung and SK Hynix have taken similar steps. The pattern points to a labour market catching up with the memory supercycle on the supply side, even as HBM pricing holds at the customer end.

The takeaway: when the largest memory makers pay out up to nearly six years of salary, the bottleneck has moved from wafers to people.

The picture that emerges is a memory industry bracing for sustained tight supply, with new entrants staking claims on different parts of the stack and incumbent vendors competing on engineering and on payroll.