Nvidia's custom-branded high-bandwidth memory, NVHBM, is recasting how the base die underneath stacked DRAM is designed and sourced, according to a brief report carried by Chinese technology outlet Expreview (超能网). The shift moves the base die from a commodity ASIC into a piece of Nvidia-specified silicon, with knock-on effects for the HBM supply chain that feeds AI accelerators such as the Blackwell and Rubin families.

What is actually changing on the base die?

Conventional HBM — JEDEC-standard HBM3E and the in-development HBM4 — uses a logic base die that performs physical-layer I/O, test and management functions. Memory makers (SK hynix, Micron, Samsung) historically sourced that base die either from third-party ASIC vendors or from in-house foundries. NVHBM extends Nvidia's own silicon IP into that base die, tightening the coupling between the GPU package and the memory stack. The practical result is a stack that Nvidia tunes for its own interconnect, power and thermal envelope rather than accept a generic JEDEC profile.

Why does the base die matter commercially?

In a stacked-DRAM device, the base die is small in area but disproportionately valuable. It carries the PHY that talks to the host processor, the row/column steering logic, and the thermal and voltage telemetry that AI accelerators rely on for sustained HBM3E throughput above 1 TB/s per stack. Whoever owns the base die owns a meaningful share of the bill of materials and a meaningful share of the architectural influence. JEDEC's HBM4 specification, which formalises a 2048-bit interface per stack, expands the base-die content further and makes the silicon a more attractive customisation target.

Who builds the stack, and who is exposed?

SK hynix remains the lead HBM3E supplier to Nvidia, with Micron qualifying additional volume and Samsung working to re-enter the Nvidia line. Under an NVHBM model, the memory makers still manufacture the DRAM layers and assemble the stack, but they design the base die to Nvidia's specification. The change adds an Nvidia-controlled IP block to a supply chain that until now has been DRAM-vendor-led. Samsung Electronics, which lost Nvidia HBM allocation in 2024 as Nvidia concentrated volume with SK hynix and Micron, faces a more complex qualification path under NVHBM because its base-die tooling and IP pedigree differ from the incumbents.

How does this connect to packaging?

NVHBM fits the same TSV-stacking and microbump assembly used for standard HBM, but the tighter Nvidia integration dovetails with CoWoS-L — TSMC's chip-on-wafer-on-substrate flow with local silicon interconnects — that already produces the bulk of Nvidia's compute dies. A co-designed base die simplifies HBM timing alignment with the GPU clocking and lifts per-package bandwidth without inflating the PHY. Industry analysts expect HBM4-based NVHBM to support 12-Hi and 16-Hi stacks with per-stack capacity in the 36 GB to 48 GB range, though Nvidia has not publicly confirmed specific stack configurations.

Where does this leave pricing and capacity?

HBM spot pricing is not publicly disclosed, but contract pricing for HBM3E has tracked several times the per-gigabit price of DDR5, according to TrendForce and other market trackers. A custom base die is unlikely to soften that premium; it concentrates the value-add inside Nvidia's stack. Capacity remains the binding constraint. SK hynix and Micron continue to add HBM wafer starts, and supply-chain reports describe HBM output as sold out for 2025 and most of 2026. NVHBM does not relieve that tightness, but it does give Nvidia more leverage over how scarce HBM3E and HBM4 bits are configured.

The next test of NVHBM will come with Nvidia's Rubin generation, widely expected to use HBM4 memory and to be the first platform where the custom base die is fully visible in production silicon. If the architecture performs as the early reporting suggests, the JEDEC base die will increasingly look like a place where the customer, not the DRAM vendor, sets the rules.