Electronics Weekly has published a video conversation with Tessent, the semiconductor test technology family that Siemens EDA develops for chip designers facing rising validation burdens at advanced nodes.

The interview format is a familiar one for the UK outlet: a studio conversation with a vendor's technical leadership, aimed at design engineers rather than investors. But the subject lands at a moment when test has stopped being an afterthought in the silicon budget. Chip-inspection, debug and DFT decisions now shape schedules and mask budgets as much as place-and-route choices do.

What is Tessent, exactly?

Tessent is the test portfolio that Siemens inherited and expanded after acquiring Mentor Graphics in 2017 for $4.5 billion. The product family covers the standard workflow that modern system-on-chip teams lean on:

• Scan insertion and ATPG for logic test
• Built-in self-test for logic and memory
• Boundary scan and board-level test
• Diagnostics and yield analysis for silicon debug

The Electronics Weekly conversation walks through how these pieces fit into the design flow, according to the video's framing, and where the pressure points sit for teams taping out dense digital devices.

Why does an interview about test matter now?

Because test economics have moved. As die sizes shrink and transistor counts climb, the cost of catching a defect after packaging — rather than at wafer sort — grows with each step of the supply chain. Tooling that lets designers embed self-test structures and pull diagnostic data from failing parts has become standard practice at leading-edge nodes, not an optional extra.

Siemens EDA competes here against Synopsys' test products and Cadence's Modus DFT family, with all three pitching tighter integration between test insertion and physical implementation. Vendor conversations like this one are part of that contest for designer mindshare.

What does the video cover?

The Electronics Weekly piece is a conversation rather than a product launch, so it skews toward engineering fundamentals: how on-chip test structures get built, what they cost in area and timing, and how teams use diagnostic feedback to drive yield learning. Readers looking for benchmark claims or roadmap dates will not find them; the value is in the practitioners' discussion of how test decisions ripple into debug schedules and production ramp.

For design teams weighing DFT strategy on their next project, the interview offers a vendor's-eye view of where embedded test earns its keep — the argument being that self-test and diagnostics shorten the loop between a failing part and an identified root cause.

What comes next?

Siemens continues to fold Tessent capabilities into its broader EDA platform, and interviews like this suggest the company sees test as a selling point in competitive tool evaluations rather than a checkbox line item. Watch for test integration claims to feature more prominently in vendor pitches as advanced packaging stacks multiple die into a single product, multiplying the number of places a defect can hide.