Streaming Scan Network Takes PCIe Into Production Test

Since 2000, Teradyne and Siemens EDA have developed joint test solutions. Their current work runs Tessent Streaming Scan Network content on the UltraFLEXplus platform through a chip’s existing PCIe interface.

Each new generation of AI and data-center silicon adds logic, cores and scan content that must reach the device for test. Chiplet packages multiply the burden because every die has separate requirements and patterns, raising pressure to keep test time and test cost in line.

What does PCIe streaming change?

Siemens’ Tessent Streaming Scan Network packetizes scan data for efficient delivery and sharing across cores. Tessent In-System Test adds an on-chip controller that accepts deterministic patterns over a standard AXI bus.

The controller allows test content to arrive through a functional interface the device already carries, such as PCIe or USB, rather than through a dedicated test port. The route uses the device’s existing high-bandwidth connection as test infrastructure.

That approach addresses the central constraint: growing pattern volume must not extend test time and raise test cost. The available details include no measured test-time saving, throughput gain or cost reduction, so the commercial benefit remains a workflow claim rather than a quantified production result.

Siemens and Teradyne describe the intended continuity this way: “One programming model carries from engineering bring-up through production.” Patterns and diagnosis flows established during design therefore remain usable at the tester.

How do Tessent and UltraFLEXplus connect?\n

Teradyne has integrated the Siemens Tessent Silicon Executable into the UltraPort server and the IG-XL software on UltraFLEXplus. The combined solution builds on a programming model test engineers already use.

Content generated in the Tessent shell flow reaches the device through UltraPort over the device’s own PCIe interface. Test setup, execution and debugging remain inside the standard IG-XL programming model.

Failure data returns in formats already consumed by the Tessent diagnosis ecosystem. Established yield-analysis and failure-analysis flows carry straight over, connecting the design environment with the production tester.

Support spans the hardware, embedded software and the integration between them. The partners present those elements as one robust solution.

What does the joint history show?\n

The companies began collaborating in 2000, when built-in self-test first met automatic test equipment. In 2019, they simplified silicon bring-up and debug on ATE through Tessent ATE-Connect and Teradyne PortBridge.

More recently, their joint work has centered on running Streaming Scan Network content on UltraFLEXplus. Siemens and Teradyne state the guiding principle: “design-for-test decisions and test execution should not be two separate conversations held by two separate teams many months apart.”

The sequence links design-for-test decisions to test execution while keeping hardware, embedded software and integration under one support umbrella. Design work can convert more directly into production test.

How do chiplets change test economics?\n

The AI buildout has changed test strategy as devices grow larger, draw more power and increasingly use chiplet assembly. A single weak die can compromise a package worth many times that die’s value.

That risk moves test-cost decisions earlier into the design flow. Teams choose design-for-test (DFT) architecture long before a device reaches a tester. The shift increases the commercial importance of alignment between design and test ecosystems.

When the DFT tool and test platform use the same interfaces, design work converts directly into production capability. The path from architecture decision to tested silicon stays short.

What changes for test teams?\n

Teradyne and Siemens list four operating effects:

• Scan content moves over a high-bandwidth interface the device already carries, keeping test time in line as pattern volume climbs.
• Bring-up and debug move faster because engineers can patch and rerun patterns inside the flow that generated them, while failure data returns in formats diagnosis tools already read.
• Deterministic EDT patterns can be applied at ATE, SLT and in-system, allowing pattern content to change as new fault models emerge.
• DFT work already completed in Tessent carries forward to the tester, bench and system, with one place to go for support.

These effects preserve one programming model from engineering bring-up through production. Patterns and diagnosis flows stay connected to the same hardware, software and integration support.

No rollout schedule, customer count, tester capacity, pricing or measured test-time reduction appears in the available information. The commercial claim therefore remains centered on continuity rather than a quantified production gain.

For upcoming AI and data-center chiplets, the competitive question is whether vendors can keep test time and cost aligned as scan patterns multiply, without breaking continuity between design and production.