Google Refashions TPU 8 Chips for Inference as AMD Lands a Socket

Google will install two reworked TPU 8 accelerators, the TPU 8tx and TPU 8i Max, starting in 2027, and the TPU 8tx replaces Google's own Axion Arm CPU with an unnamed AMD Epyc part. The variants were announced alongside a cluster revelation: Google ganged 9,600-accelerator pods into a system with more than 1 million TPU 8t devices to train the Gemini 4 Carbon frontier model.

Mark Lohmeyer, vice president and general manager of AI and computing infrastructure at Google, confirmed the pod-to-cluster structure on a conference call. Gemini 4 Carbon, developed by DeepMind, was announced on October 28, a few weeks after Gemini 4 Argon, and Google says it performs better across the board.

The base machines are not new. Google revealed the "Sunfish" TPU 8t and "Zebrafish" TPU 8i in April. Broadcom shepherds the TPU 8t, built at TSMC, and units are expected to be entering Google datacenters now. MediaTek shepherds the TPU 8i, which suffered delays earlier this year; its current shipping status is unclear. A year-long precedent supports the 2027 timeline: the predecessor Ironwood TPU v7p was deployed internally in Q4 2025, and it took roughly a year before Google could rent excess capacity on Google Cloud, with pricing posted in US-Central1 in Iowa and Europe-West2 outside London.

What changes on the training chip?

Nothing, and that is the point. The TPU 8t remains a training engine, with a 3D torus interconnect spanning 9,600 accelerators in a shared coherent memory space, delivering 121 exaflops at FP4 precision. Each TPU 8i device carries 216 GB of HBM3E across six stacks — the largest shared memory footprint in AI computing, according to Google's figures. Google wants as many of these parts as Broadcom and TSMC can supply for Gemini training.

Why the TPU 8tx exists

The 8tx variant trades the 3D torus for Google's boardfly topology, a dragonfly variant built for inference. Pod size drops from 9,600 to 1,152 accelerators. The fabric diameter shrinks 8.3X, and average latency roughly halves on the same proprietary Inter Chip Interconnect. Google targets complex agentic workloads with many concurrent inference streams. The chip can still train during idle periods.

The AMD Epyc switch is the more striking move. Google cites on-board root of trust and encryption accelerators on the AMD parts, which keep workloads encrypted until use and re-encrypt them after processing. Google has implied a custom Arm Epyc part, though the customization may amount to core count and clock speed; it could be a current Turin Epyc 9005 or an impending Venice Epyc 9006. Google already has its own security processors, and it has not explained why this function is absent from the TPU architecture and Axion. Expect it embedded in TPU 9 and next-generation Axion, which makes this possibly a short-term win for AMD.

What does the TPU 8i Max trade away?

The 8i Max doubles Zebrafish accelerator complexes per socket to attack large-context inference, but HBM capacity per socket rises only 33 percent. The original Zebrafish chip had eight HBM3 stacks totaling 288 GB at 8.6 TB/sec. Each 8i Max chip carries 192 GB at the same bandwidth, implying a shift from twelve-high to eight-high stacks. Memory per unit of compute falls, and some compute may strand. Google did not say whether it binned slower Zebrafish parts to rebalance. An unexplained difference in the ICI port at the bottom of the 8i Max board also remains unaddressed.

Pricing and TPU Sync

Pricing for the new parts is unknown. Gemini 4 models carry introductory API pricing of $2 per million input tokens and $10 per million output tokens, with cached input at 95 percent off. By analogy, expect the TPU 8tx to carry a modest premium per hour and the 8i Max to cost a little under 2X the TPU 8i rate.

Google also launched TPU Sync, a hierarchical storage management layer that moves working memory off the TPU when an agent pauses and restores it on resume. "TPUs are actually often idle a large percentage of the time," Lohmeyer said, and freeing those resources for other tasks "ultimately drives down the cost per transaction." TPU Sync is software and has been back-ported to TPU generations 5 through 8. Google has not disclosed how Sync orchestrates memory across millions of TPUs, nor how much it boosts inference throughput — two gaps worth watching as the 2027 ramp approaches.