Intel Claims EMIB Wafer Utilization Above 90% in 2.5D Packaging Push

Intel says its EMIB packaging process achieves wafer utilization above 90%, against roughly 60% for the silicon interposer approach that dominates advanced AI chips today. Lee Kyu-oh, a director overseeing packaging at Intel Foundry, presented the figures on November 4 at ISMP 2026, the International Symposium on Microelectronics Packaging, held at the Paradise Hotel in Busan, South Korea.

The claim cuts at the central cost problem of 2.5D packaging. EMIB, or Embedded Multi-die Interconnect Bridge, connects dies by placing small silicon bridges only at necessary points. A conventional design instead uses a large silicon interposer that supports the entire chip. Lee said the interposer process runs at around 60% wafer utilization, while the bridge approach exceeds 90%. That gap translates directly into cost per package. It is Intel's own number, presented at an industry conference, and not independently verified.

What is EMIB-T and why does it matter?

The variant drawing the most attention is EMIB-T, which embeds through-silicon vias inside the bridges to secure power delivery paths. "EMIB-T is an architecture that can flexibly respond to demands for larger chips by placing high-density silicon only where needed," Lee said. He added a prediction: "Considering AI semiconductor performance, embedding TSVs in all bridges will become the trend."

Customer interest appears concrete, though unconfirmed by the companies themselves. According to industry sources, two chips in Google's TPU v9 lineup — HumuFish and TriggerFish — are expected to use EMIB-T, while a third, WhaleFish, will use TSMC's CoWoS-L. Amazon is also reportedly planning to adopt EMIB-T for its own AI chips. Neither Google nor Amazon has announced these decisions publicly.

How big do AI packages get?

The scaling roadmap Lee presented is aggressive, and each step multiplies bridge count.

• Commercialized in 2026: packages up to 120x120mm, up to 12 HBM stacks, more than 20 EMIB bridges.
• Under development: 120x180mm or larger, at least 16 HBM stacks, more than 38 bridges.
• Future outlook: 240x240mm packages with more than 32 HBM stacks and more than 70 bridges.

Intel projects that once packages reach 240x240mm, bridge demand will exceed 70 per package. That projection is a roadmap, not a shipped product, and it assumes AI chips keep growing at the current pace. Notably, Intel did not disclose back-end yield figures for packages already in production — the metric that will decide whether the utilization advantage survives contact with volume manufacturing.

Where do the bridges come from?

The supply chain carries a geographic wrinkle. Silicon bridges for EMIB are reportedly produced by Taiwan-based UMC using mature 12-inch processes at fabs in Taiwan and Singapore, according to industry sources. So while Intel positions EMIB against TSMC, a Taiwanese foundry remains inside its packaging supply loop. That matters for customers weighing geopolitical exposure alongside cost.

Can Intel catch CoWoS?

TSMC is not standing still. Market research firm TrendForce projects that TSMC's CoWoS-L will integrate four chiplets and 12 HBM stacks in a 5.5-reticle-size package in 2026. By 2028, TrendForce expects the format to reach 14 reticles, holding 20 chiplets and 20 HBM stacks. Those are analyst projections, not TSMC commitments.

Industry observers say Intel's EMIB family is emerging as a realistic alternative because TSMC's CoWoS capacity remains tight. Capacity scarcity, not technical superiority, may be doing much of the selling. For EMIB to convert into actual mass-production volume, Intel still needs to secure design wins from major customers and prove back-end process yields at scale — the two hurdles Intel's Busan presentation left largely unaddressed, beyond the Google and Amazon reports it did not confirm.