In 2028, Kioxia plans to start sampling an SSD built around fast NAND fronted by a Compute Express Link controller, a device the company says will cut data-read latency to less than one-tenth that of conventional NAND.

The flash maker intends to sell the part as a CXL module riding a PCIe link. Replacing part of a host's DRAM with the module, Kioxia claims, can double memory capacity and lift performance by 30 percent.

That's a bold pitch from a company whose main product has historically lived well below DRAM in the memory hierarchy. Kioxia is gambling that the latency tax of NAND vanishes — or at least shrinks — once a CXL-aware controller brokers every read.

Why pair NAND with CXL at all?

Compute Express Link gives a host CPU a coherent, cache-coherent path into attached memory. Pair that interface with high-speed NAND and a controller that pre-stages the right pages, and the host treats the device like a slower tier of DRAM rather than an I/O endpoint.

Kioxia's "less than one-tenth" claim implies roughly an order-of-magnitude jump over a raw NAND path. Independent validation has to wait for sampling silicon. The 2028 window puts the product inside the same ramp as PCIe 6.0 and CXL 3.1 ecosystems — and inside the same procurement conversations as LPDDR and HBM.

Cadence crosses PCIe 6.0 compliance on TSMC N3

Cadence said its PHY and controller IP for the PCIe 6.0 specification — implemented on TSMC's N3 process — passed first-pass silicon at the PCI-SIG compliance workshop in late July. Its x8 subsystem hit the spec's full 64 GT/s.

It was the industry's first official compliance event for PCIe 6.0. Cadence's result lands ahead of most rival PHY vendors taping out at N3, and it gives server and accelerator designers a tested PCIe 6.0 building block for next-generation platforms.

Everspin pushes STT-MRAM into space and defense

Everspin signed a partnership with Teledyne HiRel to fold its PERSYST STT-MRAM into Teledyne's rad-hard memory portfolio for aerospace, defense and space programs. Teledyne will screen, qualify and obsolescence-manage the parts — giving customers an MRAM option for slots that historically went to NOR flash or battery-backed SRAM.

The deal broadens Everspin's footprint beyond industrial and enterprise customers. It also locks STT-MRAM into a market where long lifecycles and radiation tolerance outweigh the per-bit cost premium over NOR.

Snowflake rides the agentic-AI wave

Snowflake posted fiscal Q2 product revenue of $1.49 billion, up 37 percent year-over-year — its third straight quarter of acceleration and seven points faster than at the start of FY'27. Non-GAAP operating margin expanded more than 400 basis points to 15 percent.

• Full-year product revenue guidance raised from 31 percent to 36 percent growth
• Non-GAAP operating margin target lifted from 13.5 percent to 14.5 percent
• 692 net-new customers added in the quarter, up 32 percent year-over-year
• 828 customers now sit above $1 million in trailing-twelve-month product revenue

Snowflake framed the quarter as proof that "the Agentic Enterprise runs on Snowflake" — a slogan built to capture AI workloads that now read and write more data than the humans who configured them.

What ties the week together?

The through-line across these announcements: storage keeps climbing up the memory stack. Kioxia wants NAND inside the DRAM tier. Cadence shipped PCIe 6.0 silicon fast enough to feed it. Everspin is pushing MRAM into programs that once settled for NOR. And Snowflake is monetizing the data those tiers produce.

If Kioxia's 2028 sampling date sticks, expect CXL-attached NAND to land in the same conversations as LPDDR and HBM — not a replacement, but a third memory tier that finally has a coherent interface.