Marvell has raised the memory ceiling of its CXL expansion controllers to 9TB of DDR4 per chip, targeting AI key-value caching pools that overflow GPU high-bandwidth memory. The second-generation Structera X 3406 and 3506 support CXL 3.2 and PCIe Gen 6, up from CXL 2.0 and PCIe Gen 5 in the first generation. Sampling starts in Q1 2027.

The new parts carry six DDR memory channels, 50 percent more than the four-channel X 2404 and 2504. Each controller addresses up to 9TB of DDR4 or 6TB of DDR5. The naming scheme encodes the split: the first digit gives the CXL generation, the second the DDR generation, and the final two digits the channel count.

What problem does the added capacity solve?

AI token processing caches key-value pairs in GPU high-bandwidth memory. When HBM fills, that cache spills to server x86 DRAM, which also has hard capacity limits. CXL pools external memory and serves it across the PCIe bus to attached hosts, enlarging the effective KV cache without replacing the server.

Marvell claims the new controllers accelerate memory-bound AI workloads with up to 5x higher LZ4 compression throughput. Compression delivers 2 to 3x more effective memory capacity, improving large language model serving and deep learning recommendation model (DLRMs) performance.

CXL 3.2 support enables memory sharing across up to four hosts with up to 256 GB/s of host bandwidth. The parts include enterprise-grade RAS features and post-quantum security.

Will Chu, EVP and GM of Custom Cloud Solutions at Marvell, positioned the launch as portfolio breadth. He said: "Marvell is the only provider with a complete end-to-end CXL portfolio spanning memory expansion (Structera X), near-memory acceleration (Structera A), and PFMA (Photonic Fabric Memory Appliance), pod-scale CXL memory-sharing appliance, giving customers a complete portfolio from direct-attach to disaggregated memory pooling. We are delivering industry-leading CXL controllers, co-developed with leading hyperscalers to address the most demanding AI infrastructure requirements."

Who has committed?

Marvell said the prior-generation X 2404/2504 architecture is "already shipping to hyperscalers." Two hyperscalers have publicly backed the new generation.

An Alibaba spokesperson said: "Our collaboration with Marvell brings together its leadership in CXL technology with Alibaba's experience in large-scale AI and cloud infrastructure to develop memory architectures designed for the next generation of AI data centers."

Yashar Bayani, director of Hardware Engineering at Meta, said: "Meta is pleased to work with Marvell to advance CXL solutions that address the growing memory demands of compute infrastructure. As systems scale, increasing memory capacity while improving infrastructure efficiency and cost becomes critical. CXL provides a flexible approach to expanding memory resources and optimizing infrastructure economics."

Why now? Memory pricing

Analyst Jim Handy of Objective Analysis, author of a CXL market report, tied adoption to current DRAM market conditions. He said: "CXL is starting to gain widespread adoption in AI systems since they reap strong benefits from its very high bandwidth and support of large memory sizes. In addition, today's memory shortage and subsequent high prices are driving IT managers to use CXL to re-deploy used DDR4 DIMMs into DDR5 systems for immediate cost savings."

Handy added that managers will next use CXL memory pools to cut stranded memory, and that controllers offering compression, as Marvell's does, will prove "even more interesting" on that path.

What comes after Gen 2?

The 3406 supports DDR4 and the 3506 DDR5, letting operators tier older DIMMs into DDR5 systems during a period of tight DRAM supply. Marvell has a strong photonics focus, and the logical next step is external memory pools linked to processors over high-speed photonic interconnects. CXL would likely keep its protocol, coherency and memory semantics while adopting silicon photonics and fiber as the physical transport, with PCIe Gen 6 and Gen 7 candidates for the same optical treatment. Whether Q1 2027 sampling converts to volume shipments before that photonic shift arrives will shape Marvell's competitive position in memory expansion.