Marvell has begun sampling the Teralynx T100, a monolithic switch ASIC delivering 100.4 Tb/sec of aggregate bandwidth. The part uses TSMC's 3-nanometer process, likely the N3E variant. Rishi Chugh, general manager of Marvell's Network Switching Division, confirmed the chip to The Next Platform.

The T100 packs 512 working SerDes rated at 224 Gb/sec. Signaling overhead trims usable throughput to 200 Gb/sec per lane. Marvell physically places 608 SerDes on the die. That 19 percent overprovision absorbs yield losses on the immature N3 node.

What does the chip actually deliver?

The T100 integrates four packet processing engine blocks around a central SRAM cache. Port-to-port hop latency measures 420 nanoseconds today. Marvell engineers target the mid-300ns range after further tuning, though that figure remains a stated goal rather than a measured result from actual shipping silicon today.

What does the latency target unlock?

Reaching the mid-300ns range would let the T100 support the ESUN scale-up memory sharing protocol for AI accelerators. ESUN is positioning as an alternative to Nvidia's NVLink and NVSwitch fabric across XPU clusters of accelerators.

Marvell also bakes in Ultra Ethernet Consortium protocols. Adaptive routing functions target scale-out fabrics spanning tens to hundreds of thousands of XPUs in a single domain. The T100 runs SONiC, the Microsoft-originated open-source network operating system, alongside proprietary hyperscaler variants that Innovium originally courted from its 2015 founding and 2017 emergence from stealth.

How does T100 stack against InfiniBand?

Nvidia's InfiniBand delivers roughly 130 nanoseconds of port-to-port latency. The T100 trails at 420 nanoseconds today. Even Marvell's mid-300ns target leaves a substantial 170-nanosecond shortfall relative to InfiniBand in the most demanding AI training fabric topologies, where every hundred nanoseconds compounds across collective operations.

Per-port bandwidth comparisons favor InfiniBand's lower-radix approach. Radix comparisons favor the T100 by a wide margin. Operators requiring hundreds of ports per switch find InfiniBand's design forces heavy chaining across multiple NVSwitch devices to reach comparable aggregate capacity.

Which packaging options will ship?

• BGA, sampling Q4 2026
• Co-packaged copper (CPC), 2U 64-port 1.6 Tb/sec switch
• Co-packaged optics (CPO), with COMe X86 or Arm control plane
• Near-package optics (NPO), configuration not pictured in the source

The BGA reference platform delivers 64 ports at 1.6 Tb/sec in a 3U chassis. One variant targets Open Compute Project's Open Rack v3 with 21-inch width and bus bar power. That Open Rack v3 form factor hints strongly at Meta Platforms involvement as a likely switch ASIC customer, though Marvell declined to confirm any specific identity on the record.

What is Marvell's prior track record?

Innovium shipped 1 million 400 Gb/sec Ethernet ports in 2020 from Teralynx 7 and Teralynx 8 chips combined. Marvell acquired Innovium in August 2021 for an undisclosed sum.

By 2023, cumulative 400 Gb/sec ports exceeded 5 million. That equals over 300,000 switches deployed in just three years of hyperscale adoption. In 2024, Marvell's 51.2 Tb/sec Teralynx 10 ramped on TSMC 5nm processes, pushing cumulative 400 Gb/sec port shipments past 20 million and switch totals to approximately 1.25 million per The Next Platform's estimate.

What does Marvell claim on cost?

Marvell cites $200 million in TCO savings per "volume deployment." The company declined to define that deployment threshold for analysts. Tens of thousands of switches likely qualify based on standard hyperscaler order patterns, though Marvell withheld specifics on record.

Chugh told The Next Platform that monolithic die construction cuts power consumption by 25 percent versus equivalent chiplet designs that would deliver the same aggregate bandwidth per device. Typical T100 power sits below 1,000 watts per device. Yield on the 3nm node remains the open engineering question for any monolithic switch ASIC at this scale.

What remains undisclosed?

Marvell did not disclose T100 pricing or wafer allocation volumes. TSMC N3E capacity remains constrained industry-wide, though specific allocation figures were withheld. The T100 sample-to-volume transition through 2027 depends on those undisclosed capacity commitments and on customer ramp timelines that remain aspirational rather than contracted.

The source article also omits Nvidia's NVSwitch refresh timeline entirely. Broadcom and Cisco Silicon One roadmaps were not addressed in Chugh's commentary, which stayed exclusively forward-looking on Marvell positioning rather than reactive to competitor disclosures in the same week.

Looking ahead

Marvell enters 2026 sampling the highest-radix monolithic Ethernet switch ASIC publicly disclosed. The 3nm yield curve, not the marketing claims, will set the commercial ceiling for the T100 family.

Hyperscaler ESUN adoption during 2027 will reveal whether the part can displace InfiniBand at scale inside AI training clusters. Power efficiency rivals raw latency as a buying criterion in those fabrics.