Memory Sold Out Through 2029 as HBM Squeeze Reshapes AI Supply

SK hynix expects memory supply constraints to persist through 2030, with its DRAM and HBM volumes effectively sold out through 2029. Samsung takes a similar view, forecasting tight supply through 2028 and confirming that its 2027 HBM output is already spoken for.

The shortage has a structural explanation. Samsung cites lengthy fab construction and equipment lead times, larger dies, greater process complexity in next-generation HBM, and a steady shift of DRAM capacity toward HBM. Demand is not the question; supply is.

The money is now following the scarcity. Solidigm, SK hynix's U.S. subsidiary, is reportedly discussing a proposed $45 billion NAND flash fab with the U.S. Commerce Department. China's CXMT plans to begin limited production of HBM3E soon, despite manufacturing yields of just 20% to 30%, per Reuters.

What happens to packaging prices?

TSMC is reportedly considering a 20% price increase for CoWoS advanced packaging as AI demand strains capacity. Applied Materials plans to raise its stake in Dutch assembly-equipment maker Besi to roughly 20%, extending a partnership beyond hybrid bonding into new interconnect architectures for AI.

Advanced packaging has become the bottleneck that pricing power follows. The chiplet era made the package a fabrication problem, and the invoice now reflects it.

Where is the new capacity going?

Infineon will invest €1.1 billion through 2034 at its Villach, Austria site to build Europe's first high-volume fab for next-generation GaN power semiconductors on 300mm wafers. UMC approved an additional $3.2 billion in capital spending to accelerate expansion in Singapore and Tainan, driven by demand for advanced packaging and silicon photonics.

Intel Foundry, meanwhile, reported better yields and cycle times on its 18A process in Q3, released its 14A 0.9 PDK in October, and continues to court external customers for 18A-P and 14A while advancing EMIB-T packaging. Lam Research and imec expanded their collaboration on 3D integration, next-gen memory, and high-NA EUV patterning, including Lam's Aether dry resist technology.

Who is buying whose accelerators?

Google's TPU business is widening. OpenAI reportedly plans to purchase Google TPUs, per The Information, and Oracle will offer the accelerators through its cloud starting in 2027, adding Arm's AGI CPUs in fall 2027. Broadcom's XPUs and networking gear will support Anthropic's infrastructure expansion from 2027 under a $63 billion financing arrangement. Meta is deploying more Nvidia and AMD infrastructure, with both chipmakers taking stakes in the company.

Advantest posted quarterly revenue of ¥477.7 billion, up 82% year over year, on robust tester demand for AI. When test equipment grows at that pace, the production line behind it is running hot.

Which deals are confirmed?

Intel plans to acquire Classiq, a developer of automated quantum algorithm synthesis software, which Intel says completes a full quantum stack alongside its silicon spin-qubit technology. Two other deals remain unconfirmed: Bloomberg reports Marvell is in advanced talks to buy optical components maker Lumentum, and The Information reports onsemi is negotiating to acquire Ferric, a startup building integrated voltage regulators for AI processors, for nearly $1 billion.

What else moved this week?

• Vietnam's first fab, the estimated $1.3 billion Viettel project, may miss its 2027 trial-production target; construction has reportedly not begun and ASML lithography negotiations remain unresolved, though Viettel insists the schedule holds.
• ITIF says the U.S.-led Pax Silica initiative has grown to 26 countries coordinating on semiconductors, critical minerals and AI infrastructure.
• Infineon launched AI power-delivery technology including a ±400 V/800 V rack power-distribution reference board and 900 V monolithic bidirectional GaN switches.
• PsiQuantum demonstrated an 8×8 optical circuit switch on silicon photonics for AI infrastructure.
• TetraMem taped out a 12nm analog in-memory computing SoC using multi-level RRAM and Synopsys cloud EDA tools.
• TU Munich researchers built neural-network transistor models for 3nm nanosheet devices, cutting standard-cell characterization time by up to 8× with delay errors below 0.11%.

On security, TianoCore disclosed a critical memory-corruption flaw in EDK II UEFI firmware allowing unauthenticated code execution during PXE boot, and Supermicro disclosed nine BMC firmware vulnerabilities. NIST finalized its roadmap for transitioning federal systems to post-quantum cryptography. Cadence will supply U.S. DOE National Laboratories with EDA, multiphysics simulation and 3D-IC workflows, and separately introduced domain-specialized AI models for agentic chip design, while Arm released a CPU benchmarking methodology for agentic AI workloads.

With HBM committed through 2029 and packaging prices heading upward, the industry's next constraint is less a matter of demand than of who can bring capacity online first.