Micron has developed a 512 GB DDR5 RDIMM that enables up to 12 TB of DDR5 DRAM inside a single 24-slot dual-socket server, with volume production scheduled for the second half of 2027.

The module reaches 9,200 MT/s and cuts operating power by more than 60 percent compared with four 128 GB RDIMMs. AMD and Intel are both validating the part for next-generation server platforms. For Spark SVM-based analytics, Micron says the part delivers up to 1.4x the performance of a 256 GB DDR5 configuration.

Doubling per-slot density matters because AI training and inference routinely hit memory ceilings before they hit raw compute ceilings. Validation paths at both AMD and Intel give the module a route into the x86 server generations shipping in 2027 and 2028.

What chips are joining the inference race?

French fabless startup VSORA has moved its inference accelerator into volume manufacturing at TSMC. The chiplet pairs 288 GB of HBM3E memory with 3,200 TFlops of compute, and the company says its architecture shortens the path between processing and memory.

Two chiplets combine into a 2U server node rated at 26 PFlops and 2.3 TB of HBM3E. A reference rack reaches up to 5 PFlops and 18.4 TB of HBM3E. Customers compile models onto the device through the VSORA SDK, and general commercial availability is expected by year-end.

Inference efficiency is also the focus of Cambridge, Massachusetts, startup Subconscious. The company says its OrangeLine runtime compresses agent context directly on the GPU rather than the usual summarize-and-discard path, holding 5 million-plus tokens while delivering 2.3x more concurrent work on the same GPUs. Founder Jack O'Brien said: "Our biggest draw is helping our customers achieve longer-running sessions at lower costs. We compress the context window at runtime, so a long agent run stops carrying dead weight, and the model stays fast deep into the job."

What is changing at the flash tier?

Samsung's PM1753 enterprise SSD family is now on Cloudian's HyperStore supported drive list. The PM1753 is a PCIe 5.0 x4 drive available in 1.92 TB to 30.72 TB capacities and 2.5-inch, E1.S, and E3.S form factors. Samsung rates sequential read at up to 14,500 MB/s and sequential write at 10,000 MB/s, with random read at 3,300K IOPS and random write at 650K IOPS at 1 DWPD over five years.

Cloudian reports that demand for flash is rising as AI workloads move into object storage, even with NAND prices elevated. Some customers are pairing a flash front end with an HDD layer behind it. The PM1753 puts Samsung's PCIe 5.0 enterprise line in direct competition with Kioxia, Micron, and Solidigm in AI-adjacent object deployments.

What does the new memory tier look like?

ADATA unveiled TRUSTA AI Scaler Extended Memory at the USA AI Infra Summit 2026. The product pools GPU memory, DRAM, and SSD resources to let larger models run on systems with constrained GPU memory. ADATA claims it can cut deployment costs for inference and fine-tuning by more than 50 percent versus GPU-only systems. The free, open source AI Scaler Toolkit supports Llama, Qwen, Mistral, GPT-OSS, DeepSeek, Phi, and Gemma.

The disclosure that TRUSTA is not an Nvidia KV cache implementation narrows its scope to on-premises inference and fine-tuning. ADATA has positioned the system where buyers want memory expansion without committing to one accelerator vendor's caching scheme.

Where does this leave the supply picture?

The 512 GB RDIMM, the VSORA chiplet, and the PM1753 SSD all chase the same problem: feeding accelerators that are now faster than the memory and storage around them. ADATA's tiering product approaches the gap from the system side. Competitive pressure on Micron, Samsung, and SK Hynix will likely show up first in module density and per-watt bandwidth, then in high-capacity pricing through 2027.