MIPS Ships RISC-V Reference Hardware for Physical AI Robots

MIPS is now shipping three RISC-V reference platforms — Actus-1, Acies-1 and Aegis-1 — that push 50 TOPS of AI acceleration at 10 W, marking the IP vendor's move from licensable cores into physical hardware for robotics developers. The company confirmed the designs at electronica 2026 coverage published by Electronic Design.

MIPS built its business on RISC-V IP, from hard real-time cores to cores that run large language models. Customers normally fold that IP into custom silicon. Simulation can evaluate a design, but real hardware shortens the loop. The new platforms serve that gap.

What are the three platforms?

The suite targets evaluation and prototyping, not final products:

• Actus-1 — a module for real-time motor control and communication.
• Acies-1 — an M.2 card adding AI acceleration, including LLM support.
• Aegis-1 — the central controller board, built to run an OS such as Linux and orchestrate a complete physical AI system.

The platforms combine modules, M.2 cards and motherboards. MIPS says they target physical AI and robotics first, but any embedded application can use them. The designs implement RISC-V profiles such as RVA23 and, on the real-time side, RVV-era vector profiles including RMV23-class cores.

How does Actus-1 handle motor control?

Actus-1 pairs two MIPS Atlas M8500 real-time RISC-V cores with an ARC VPX 512-bit vector processing unit. GlobalFoundries manufactures the module on its FDX FD-SOI process, and on-chip MRAM provides non-volatile storage — a combination aimed at systems seeking ISO 26262 and ISO 21434 certification.

The module handles field-oriented control directly. It carries 100-picosecond-class high-resolution PWM generation plus a sigma-delta ADC. A gigabit Ethernet port feeds a three-port switch with time-sensitive networking support. USB, CAN-FD, SPI and I2C interfaces round out the module.

FD-SOI and MRAM are deliberate choices. Both suit safety-critical and power-constrained motor control, where flash write endurance and radiation tolerance matter. MIPS did not disclose pricing or volume availability.

Where do the 50 TOPS come from?

The Acies-1 M.2 module carries the MIPS Atlas S8200, an RISC-V RVA23 platform with RVV vector extensions and VME vector matrix extensions. MIPS quotes 50 TOPS from eight cores, with over 50 GB/s of bandwidth, all within a 10 W power budget.

The module runs LLMs including Llama.cpp and Qwen, plus vision-language-action models. It supports integer and floating-point weights, including FP4 — the lowest-precision format now common for edge inference. MIPS did not publish pricing or shipment dates.

Software support comes through the Atlas SDK and Graph Performance Simulator. The toolchain includes an IREE-based MLIR compiler that accepts TensorFlow, PyTorch and ONNX models.

What does the controller board add?

The Aegis-1 board anchors the stack. A multi-core ARC-V RPX-500 processor runs agentic workloads and hosts Linux. Alongside it sit an Atlas M8500 safety processor, an ARC RHX-100 security processor and an Atlas S8200 neural processing unit. MIPS says the board addresses ISO 26262, ISO 21434 and the European Union's Cyber Resilience Act.

An Atlas I8500 integer RISC-V core manages Ethernet, again with TSN support. PCI Express, USB, SPI and other standard serial and parallel interfaces connect peripherals.

Does hardware change the IP business?

The move is modest but telling. Reference hardware lets developers measure real power and latency before committing to custom silicon, which IP vendors usually leave to partners. MIPS has not said whether the platforms will become product families or remain evaluation tools. The 10 W envelope for 50 TOPS, if it holds on customer benches, will define how competitive Atlas-class cores become against established edge NPU vendors.