A study published in Nature reports that controlling surface kinetics during growth allows p-type two-dimensional semiconductors to be scaled — a result aimed at one of the most stubborn bottlenecks in post-silicon device research.

The paper, titled "Controlling surface kinetics scales p-type two-dimensional semiconductors," addresses a materials problem that has constrained complementary logic built on 2D channels. While n-type 2D semiconductors have progressed steadily, their p-type counterparts have lagged, largely because growth and contact formation for hole-transporting films have resisted the uniformity and scale that wafer-level manufacturing demands.

The researchers' central claim is mechanical and specific: by governing how atoms behave at the growth surface — the kinetics of arriving species and how they settle into the crystal — the team could produce p-type 2D semiconductor films that scale beyond the small, lab-scale flakes that dominate much of the field's published device work.

Why does p-type scaling matter?

Complementary metal-oxide-semiconductor (CMOS) logic needs both electron and hole conduction. That symmetry, taken for granted in silicon for decades, has never been routine in the 2D-materials world. Graphene, MoS2 and related transition-metal dichalcogenides have yielded credible n-channel transistors, but p-channel equivalents have suffered from poor contacts, low mobility and non-uniform growth.

Without scalable p-type films, any roadmap toward 2D-channel CMOS — the successor technology candidate that imec, TSMC and Samsung Research have publicly flagged for exploratory nodes beyond the mid-2030s — remains incomplete. A growth method that closes the p-type gap changes the competitive calculus for those programs, though the Nature result is a materials demonstration, not a manufacturable transistor process.

What does surface kinetics control actually change?

In conventional thin-film growth, temperature and precursor flow set the broad conditions. Surface kinetics — the rates at which adatoms attach, migrate and desorb — determines whether a film grows layer-by-layer with the registry the crystal needs or degenerates into islands and defects.

For p-type 2D semiconductors, the problem has been acute: the same growth windows that produce usable n-type crystals often fail for the hole-transporting compounds, and post-growth doping or contact engineering has partially compensated without delivering uniformity. The Nature study's approach treats kinetics as the control variable, so the film's electronic quality is set during growth rather than repaired afterward.

That distinction matters commercially. Post-growth repair steps add mask layers, thermal budget and yield loss at scale. Growth-time control, if it transfers to industrial tools, would slot into existing deposition and anneal sequences more cleanly.

What remains unproven?

The publication establishes the growth principle and its scaling behavior. It does not, on the evidence of the title and abstract-level claims, establish:

• Wafer-scale uniformity on 300 mm substrates
• Transistor performance metrics comparable to silicon or silicon-germanium p-FinFET/p-GAA channels
• Contact resistance figures low enough for low-power logic
• Integration with high-κ dielectrics at back-end-of-line thermal budgets

Each of those gaps is where a laboratory result in Nature and a process-of-record at a leading-edge foundry diverge. History offers a caution: high-mobility channel candidates including III-V materials followed a similar laboratory-to-fab path and took more than a decade to reach limited production insertion.

How should fabs and equipment makers read this?

For fabs, the result is a watch-list item: it strengthens the case that 2D-channel CMOS can be symmetric, which is a precondition for any serious insertion roadmap. For equipment suppliers — Aixtron, AIXTRON SE's MOCVD lines, Applied Materials' epitaxy portfolio, and the CVD toolmakers who would carry such processes — a kinetics-controlled growth recipe points toward tighter in-situ metrology and faster precursor switching as differentiators.

For now, the Nature paper stands as peer-reviewed evidence that the p-type barrier in 2D semiconductors is a growth-kinetics problem that can be engineered around — and that scaling it is now demonstrated at the research scale rather than merely proposed.