Nature has published a feature on 2D semiconductors aimed at accelerating high-performance electronics, framing atomically thin materials as a parallel track to silicon CMOS scaling at advanced nodes.

The article, in Nature, surveys two-dimensional (2D) materials — crystalline sheets one to a few atoms thick — as candidates for transistors, interconnects, and stacked heterostructure devices. The framing reflects a long-running research bet across academia and industry: 2D channels preserve useful electronic behavior at thicknesses where bulk semiconductors, including silicon and III-V compounds, lose mobility and gate control.

What does 2D semiconductor mean for chip design?

Two-dimensional semiconductors refer most often to transition metal dichalcogenides (TMDs), hexagonal boron nitride, and similar layered crystals. Molybdenum disulfide (MoS₂) and tungsten diselenide (WSe₂) are the most studied for transistor channels because they combine usable bandgaps with adequate carrier mobility at sub-nanometer thicknesses.

Engineers value these materials for three properties:

• Atomic thinness, which supports sub-5 nm gate lengths without short-channel effects
• A native bandgap at monolayer thickness, a property graphene lacks
• Layer-by-layer stacking to engineer heterostructures impossible in bulk silicon

Where does the technology sit today?

The 2D transistor field remains in research and pilot-line work, not high-volume manufacturing. Wafer-scale monolayer growth, low-resistance ohmic contacts, and integration with silicon back-end-of-line processes are the unresolved engineering problems. None of the top-tier foundries — TSMC, Samsung Foundry, or Intel — list 2D channels on production roadmaps through 2030. The 3 nm and 2 nm nodes now ramping at TSMC, with Samsung and Intel tracking closely, stay on silicon-channel finFET and gate-all-around (GAA) architectures.

Why the chip industry keeps watching

Two motivations keep 2D materials on industry watchlists:

• They could extend MOSFET scaling past the point where silicon channels lose electrostatic integrity at sub-2 nm gate lengths
• They enable device topologies inaccessible in bulk semiconductors, including ferroelectric field-effect devices, tunnel-FET and negative-capacitance structures, and room-temperature quantum-effect circuits

The second motivation carries more weight in research labs than in fabs. None of the exotic applications have moved beyond bench-scale demonstration.

What changes if 2D reaches production?

If 2D-channel transistors enter high-volume manufacturing, supply-chain impact lands first in deposition, lithography, and metrology. CVD and MOCVD tool vendors would need atomic-layer systems tuned for TMD growth on 300 mm wafers. Lithography suppliers would see demand grow for EUV and advanced patterning tuned to sub-2 nm features on monolayer films. Metrology specialists would face new defect-inspection challenges that existing optical and e-beam tools cannot fully resolve.

Today's 300 mm fabs and 2 nm-class process flows are not designed for 2D integration. Adoption would require parallel tool development, not retrofit.

The road from lab to fab

The Nature coverage signals sustained scientific attention on 2D semiconductor research. Whether that work translates into a manufacturing technology will depend on solving wafer-scale growth, contact resistance, and CMOS integration — three problems that have kept the field in research labs for more than a decade.