A research group has fabricated boron carbon nitride (BCN) at wafer scale and demonstrated p-type semiconductor behavior, addressing a longstanding gap in the material set available for two-dimensional (2D) chip integration. The work, reported on Bioengineer.org, describes BCN as a candidate p-type counterweight to the n-type 2D semiconductors that researchers have already demonstrated at wafer scale.

Why p-type 2D materials have lagged

Two-dimensional semiconductors enable sub-nanometer channel thicknesses and continued gate-length scaling once silicon runs out of room. Researchers have produced working n-type 2D transistors for several years. Functional p-type 2D devices, however, have been harder to stabilize at wafer scale. Most contact and doping schemes that work on n-type channels do not transfer cleanly to p-type channels. The result is asymmetric performance that blocks complementary logic and limits the kinds of circuits designers can build on a 2D platform.

What the reported work claims

According to the Bioengineer.org summary, BCN now provides p-type behavior at wafer scale. The composition sits in the same hexagonal lattice family as hexagonal boron nitride (h-BN), a dielectric already in widespread 2D research use. BCN adds carbon atoms into that lattice, which the report credits with shifting the electronic structure toward p-type conduction while preserving the dielectric-adjacent properties of h-BN.

Wafer-scale production is the headline claim. Most 2D demonstrations stop at exfoliated flakes a few hundred micrometers across. Scaling to a full wafer — typically 300 mm in CMOS-compatible fabs, though the report does not specify a wafer size — is a prerequisite for any insertion into a commercial logic or memory back-end-of-line (BEOL) process.

How the material fits a 2D stack

A complementary 2D logic flow needs both carrier types. Without p-type channels, designers cannot build CMOS-style inverters, ring oscillators, or static random-access memory bitcells on 2D materials. The same logic applies to analog blocks, where matched p- and n-channel pairs drive transconductance.

BCN's lattice compatibility with h-BN also matters for interlayer dielectric use. If BCN can perform as both a channel material and a gate stack component, it could reduce the number of distinct materials a fab must deposit inside a 2D monolithic stack. That would simplify interface engineering in a research setting where every new heterojunction introduces defect states.

What remains unclear

The report does not state carrier mobility, on/off current ratio, threshold voltage, or contact resistance values for the BCN transistors. It also does not disclose the wafer size used in the demonstration or whether the material was grown by chemical vapor deposition (CVD), metal-organic CVD (MOCVD), or another method. Those details will determine whether BCN can match the device-level metrics that foundries require for BEOL integration. Independent replication at an industrial line remains the next gate a new 2D semiconductor must pass before it can enter a process design kit.

What it would take to reach production

Insertion into a CMOS fab typically requires a growth temperature below the thermal budget of a finished front-end wafer, a constraint that defines the upper limit for any back-end-of-line candidate material. The film also needs atomic-scale uniformity across a full wafer, plus defect densities low enough to support scaled channel lengths. A research demonstration on a smaller wafer does not, on its own, satisfy any of those constraints.

Memory applications present a different route. Three-dimensional NAND and emerging selector devices have tolerated materials that logic processes rejected, which can give a new 2D film a foothold before it scales to high-performance logic. The BCN team has not indicated which application path it is targeting.

Outlook

BCN now joins a small list of 2D materials with reported wafer-scale p-type behavior. Whether it moves from research demonstration to foundry insertion will depend on the device-level data the group reports next, and on whether other groups reproduce the result on production-grade wafers.