Intel's Packaging Technology Gains Nvidia's Interest, Easing Pressure on TSMC's Backend Operations - BigGo Finance

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Nvidia Eyes Intel Packaging, Pressure Eases on TSMC CoWoS Lines

Nvidia is in early talks with Intel over advanced packaging for future accelerators, per a BigGo Finance report — a move that could crack the CoWoS bottleneck capping AI chip shipments if it lands.

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Rebecca Stone
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Nvidia is in early talks with Intel about packaging some of its future accelerators, according to a BigGo Finance report published this week.

The development, if it lands, would mark the first major external customer win for Intel Foundry's back-end business. It would also loosen the CoWoS chokehold that has capped AI chip shipments for two years.

The Taiwan-headquartered financial outlet framed the talks as Nvidia shopping for a second packaging source beyond TSMC. No deal value, no process node, no tape-out date, no on-record Nvidia comment.

What packaging does Intel actually run?

Intel Foundry operates EMIB — its embedded multi-die interconnect bridge — out of facilities in Oregon and Arizona. The unit has also been qualifying FOPLP, fan-out panel-level packaging, pitched as a cheaper alternative to silicon interposers.

Neither line runs at CoWoS scale today. Both, however, are credible hedges for a customer looking to de-risk a single-source bottleneck.

Are the technologies drop-in substitutes?

No. CoWoS, particularly the silicon-interposer CoWoS-S variant, has become the default for high-bandwidth memory stacks paired with large AI dies across Nvidia's data-center lineup and AMD's Instinct accelerators.

EMIB uses a small silicon bridge embedded in the organic substrate, which costs less per package but caps die-to-die bandwidth. FOPLP targets larger panel formats for cost, not bandwidth.

Nvidia would need to qualify whichever Intel line it touches, a process that typically runs nine to twelve months.

What changes for TSMC?

The Taiwanese foundry has spent two years expanding CoWoS capacity to keep pace with AI accelerator demand. Even with that expansion, packaging has remained the gating step in the AI chip supply chain.

A partial Nvidia offload frees CoWoS slots for the rest of the queue — competing accelerator vendors, custom ASIC programs, the in-house silicon teams at the major hyperscalers. Slot allocation has skewed Nvidia-favored for two product cycles; any rebalancing reshuffles the revenue mix.

What changes for Intel?

A Nvidia engagement would be the first marquee external customer for Intel Foundry's advanced packaging since the unit was carved out as a standalone reporting segment.

Intel has disclosed growing — but still small — packaging revenue in its foundry segment. A Nvidia win shifts that ratio overnight, and gives the foundry's back-end story the marquee logo it has so far lacked.

What changes for Nvidia?

Portfolio insurance. The company has effectively run a single-source packaging strategy for its data-center accelerators, and that strategy worked — until capacity, not silicon, became the binding constraint.

A second vendor shifts Nvidia's negotiating posture with TSMC on CoWoS pricing and slot allocation. It also diversifies a single point of failure in a supply chain that has, until now, been one capacity wave away from a bottleneck.

What's the forward angle?

The BigGo report is thin on specifics, and Nvidia has not commented publicly on the talks. The next hard data points will be:

  • TSMC's CoWoS utilization disclosure in its Q3 earnings call
  • Intel Foundry's packaging segment revenue in its next quarterly filing
  • Whether Nvidia confirms, denies, or ignores the report at its next analyst Q&A

If the report holds, the AI industry's most stubborn supply ceiling rises — even by a little.

Source: Google News: TSMC

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Rebecca Stone

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Correspondent covering technology and product news in Semiconductors, chip manufacturing, hardware, AI compute at Chip Dispatch.

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