Samsung cuts chip simulation from 18 hours to 17 seconds on GPUs

By Tom Whitfield

Samsung Electronics said it reduced a chip-level thermal and mechanical simulation from about 18 hours on a 32-core CPU to 41 seconds on one Nvidia H100 GPU and about 17 seconds on four H100s. Samsung presented the result at Nvidia AI Day Seoul at COEX on Nov. 9, according to Korean press accounts.

The measured comparison had three points:

• About 18 hours on a 32-core CPU
• 41 seconds on one Nvidia H100, which Nvidia described as roughly 1,600 times faster
• About 17 seconds on four H100s, a roughly 3,800-times gain reported by DigiTimes

What do the headline figures show?

At the same event, SK hynix said its full-chip thermal and deformation analysis ran more than 30 times faster than its conventional CPU method. Its AI model for predicting etch profiles ran dozens of times faster than standard simulation.

Kim Jung-han, who leads the TCAD Intelligence team at SK hynix's Future Technology Research Institute, said: “As the steps increase, the number of cases grows exponentially.” Multi-step etch processes have more than 10 input variables per step, including pressure, temperature and gas flow.

These figures cover individual calculations under test conditions. Edaily noted that Nvidia's 1,600-times result applies only to the conditions tested, not to chip development as a whole, and neither company supplied data on production yield or time to market.

The evidence establishes much faster computation for selected workloads, not yet a shorter commercial chip-development cycle.

How did Samsung reach the result?

Samsung engineer Lee Sung-yeop, of the semiconductor division's CS team, said the company did not obtain the speedup by moving the same code from a CPU to a GPU. The team split a large chip into small regions, then used AI to predict representative, or homogenized, material properties for each region.

Samsung solved that representation on a coarser computational grid and ran the calculation on GPUs. An in-house algorithm reduced errors between neighboring regions, allowing the divided model to retain the reported accuracy.

The models used Nvidia's open-source PhysicsNeMo framework and Warp. Samsung also said a model trained on thermal analysis and then retrained for mechanical conditions performed better than one trained from scratch. The analysis helps engineers anticipate defects caused by heat or warping.

Samsung also said it was working with Nvidia's cuISS and cuDSS libraries for TCAD, or technology computer-aided design. Nvidia's cuEST sped some quantum chemistry calculations on Samsung's sMOL materials platform by up to five times. Its next step is engineering agents that connect simulation tools and AI models to compare design options, a roadmap rather than a measured production gain.

Model redesign, regional decomposition and error control produced the result; hardware alone did not explain it.

How did SK hynix scale its modeling?

SK hynix trained PhysicsNeMo models on its own simulation data. It reused results computed for small regions and split full-chip runs across GPUs, with performance rising nearly in proportion to the number of GPUs.

The company presented the work under a multiyear partnership with Nvidia announced in June. The agreement names CUDA-X libraries and PhysicsNeMo for TCAD workflows, alongside SK hynix's in-house engineering codes.

Kim's explanation matters because each added etch step multiplies the design cases that engineers must evaluate. Regional reuse and parallel GPU execution offer a way to limit that computational expansion without abandoning the full-chip model.

For chip modeling, the practical gain comes from reusing regional results and scaling work across GPUs.

What does this change for the HBM market?

Both Samsung and SK hynix are competing to supply high-bandwidth memory, or HBM, for AI accelerators, a market where MLQ.ai reports they now earn record margins. Faster thermal and etch modeling could support more efficient product development, but the presentations did not establish manufacturing-yield or scheduling gains.

Neither presentation offered wafer-capacity or pricing data. The immediate commercial evidence therefore lies in engineering speed, while effects on output and customer supply remain unmeasured. On present evidence, faster simulation is a capability, not yet a proven production advantage.

Going forward, the competitive question is whether these test-condition gains can become repeatable HBM design workflows that improve yield or shorten development time. Neither Samsung nor SK hynix has yet disclosed the resulting commercial effect.