SK hynix plans to put a hundred or more low-level processing cores, called H-TPUs, into future SSD controllers. The move offloads repetitive read and write work from the main controller CPU as PCIe bus speeds double with each generation.

The Elec, a Korean media outlet, reports that Korea's second memory and NAND supplier is preparing for PCIe 6, 7 and 8, where each standard doubles the throughput of its predecessor. A single controller CPU cannot keep up with the rising read and write IO demands of higher capacity and faster buses. SK hynix concluded the CPU would need to grow beyond practical physical size and power limits.

The company's answer is disaggregation. Koo In-je, SK hynix vice president of system-on-chip design, told the International SoC Design Conference (ISOCC) 2026 in Incheon, Korea: "SK Hynix decomposed the read and write processes of traditional SSD controllers into smaller tasks and structured the system so that numerous small H-TPUs process them in parallel."

The name is a coincidence of engineering, not branding alignment. H-TPU stands for Hynix-Tensor Processing Unit and is unrelated to Google's AI-focused TPUs.

What do the H-TPUs do?

Each H-TPU is a physically small, specialized core. The assigned tasks cover the low stack:

• low-level and repetitive read/write command processing
• metadata management
• buffer control

The main controller CPU keeps the high stack: storage-policy management, error recovery and exception handling.

The area and power numbers are the concrete story. One H-TPU occupies 4 percent of a standard general-purpose CPU core's area. SK hynix uses ARM Cortex-R8 CPUs in its latest SSDs. Power draw per H-TPU runs at about 2.5 percent of a standard core. Idle cores enter a low-power state when inactive.

Each core has a 4-stage pipeline and a sequential execution design. The cores receive specialized functions for their assigned tasks rather than general-purpose instruction handling.

Which products get the new cores?

The Elec understands SK hynix will deploy H-TPUs in next-generation enterprise SSDs and Storage Next SSD controllers. The affected product families include:

• AIN P, the high-performance line
• AIN B, the high-bandwidth line
• AIN D, the high-capacity line

The technology will likely also appear in the SK hynix-Sandisk High-Bandwidth Flash (HBF) platform, according to the report.

Why the architecture shift matters

The change follows a simple engineering constraint. A monolithic controller that handles all processing for high-capacity drives on PCIe 6, 7 and 8 would need more silicon area and power than the package can practically supply, so parallelism at the task level replaces a bigger single CPU.

The approach also mirrors a broader industry pattern of domain-specific acceleration, but inside the drive rather than the data center. SSD controllers have historically balanced one or two main CPUs with fixed-function accelerators for error correction and encryption. SK hynix is extending that model across the entire I/O path with programmable miniature cores.

The presentation at ISOCC 2026 marks the design as an active roadmap item rather than a shipped product. No production timeline, wafer volume or capacity figure was disclosed at the conference.

Deployment in the AIN enterprise families and the Sandisk HBF collaboration will show whether a hundred small cores can hold latency and power budgets as PCIe 6 controllers reach the market.