Study: fan-out panel packaging reaches 86% substrate utilization

By Tom Whitfield

A 300 mm fan-out panel achieved 86% substrate utilization with 12 packages in the cited study, compared with about 55% utilization and six packages on a 300 mm wafer. A 510 × 515 mm panel in that comparison carried 30 packages at 74% utilization.

These figures explain why fan-out panel-level packaging (FOPLP) has drawn interest for scaling advanced packaging production. AI packages are growing larger and integrating more high-bandwidth memory (HBM) and high-performance chips, while teams must establish stable process conditions and reach high-volume manufacturing (HVM) quickly.

High yield remains critical, but success depends on the speed of that transition. The gain carries a lithography penalty: larger panels can produce pattern distortion, die shift and overlay errors, and panel-scale variation does not behave uniformly across the substrate.

Why does panel-size lithography make yield harder?

Process engineers must find the "sweet spot" between overlay yield and throughput, the analysis says. Conventional wafer-based correction cannot address every local variation on a panel.

• Global correction preserves throughput but leaves localized overlay errors.
• Zone correction produced 40% to 80% yields in the study's field data, though throughput fell.
• Die-by-die correction can improve yield further but carries a significant throughput penalty.
• Site-by-site correction offers a compromise between yield improvement and throughput.

Finding that balance requires repeated tests of exposure field configurations, die layouts, panel layouts and overlay thresholds. Each change can trigger another trial and another data review, consuming materials and engineering time while pushing back production. Trial-and-error is therefore a commercial problem, not just a development inconvenience.

How does prediction shorten lithography learning?

Manufacturers can combine offline metrology measurements with yield prediction algorithms before using production hardware. Metrology captures panel-scale variation, including pattern errors and die shifts; algorithms test that information against exposure field configuration, panel layout, die layout and overlay thresholds to estimate yield. Engineers can then compare alternative process strategies without running full production experiments.

Heat maps, vector plots, histograms and yield dashboards expose process sensitivities, isolate variation and point to underlying causes. Figure 1 compares X-axis and Y-axis overlay errors and finds the most significant errors on the Y axis, linking them directly to yield loss. Those views let engineers target corrective action instead of repeating broad experiments.

The practical gain comes from testing process windows on data before testing them on substrates.

How accurate are the predictions in production?

A test on production substrates in an HVM process initially showed differences of 1.2% to 2.7% between predicted and measured yield. Manual inspection judgment accounted for most of that gap, according to the analysis. Standardizing the inspection process reduced prediction errors to 0.2% to 0.8%.

One implication matters for production: a small reported yield gap can reflect inconsistent inspection, not a weak model. Standardized measurements give engineers a more reliable baseline for choosing corrections.

How can qualification happen sooner?

During process development, engineers can simulate process conditions before running qualification substrates. They can compare multiple parameter combinations, shortlist promising operating windows and then validate those choices on physical substrates, rather than testing every combination on production hardware.

Figure 2 uses residual overlay error vector maps under different conditions to refine the process and reduce trial-and-error iterations. That approach concentrates engineering time on optimization rather than repetitive experiments.

Qualification still requires physical evidence, but simulation can decide which evidence to gather.

What changes when FOPLP reaches mass production?

Yield prediction can run inside the lithography workflow for real-time, in-line monitoring and earlier defect detection, as Figure 3 shows. Final inspection still determines overlay yield, but earlier steps can introduce errors that cause rework or permanent yield loss. Moving prediction earlier gives engineers time to intervene and can reduce the manpower, time and cost of rework.

Development and production then share the same control logic: measured panel variation sets a process window, and prediction checks whether the window still holds. That is a mechanism for protecting yield as FOPLP capacity comes online, not merely a research shortcut.

What does this mean for capacity and cost?

The cited numbers establish a substrate-efficiency advantage and show that prediction error can narrow once inspection is standardized. They do not quantify package pricing, production capacity or the number of iterations removed, so the size of the cost saving remains unproven.

As AI-package demand rises, the commercial test is whether faster process learning and earlier defect detection produce steadier high-volume capacity at lower cost per package. No timetable or price change is stated, and the result depends on manufacturers converting prediction accuracy into stable process conditions.