AI & Compute

Surface Code Runs On IBM's Heavy-Hex QPU, Nature Study Finds

A Nature paper from Quantum Elements and USC maps the standard surface code onto IBM's 133- and 156-qubit Heron processors, achieving directional subthreshold scaling on heavy-hex hardware.

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Rebecca Stone
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The 133- and 156-qubit Heron processors from IBM just proved they can run the surface code at scale — a result published this month in Nature that loosens a long-standing constraint on quantum processor design.

A team from three-year-old startup Quantum Elements and the University of Southern California mapped the standard two-dimensional surface code onto Heron's heavy-hex honeycomb lattice, achieving directional subthreshold scaling. Errors fall as the code grows. That's the threshold any fault-tolerant architecture has to clear.

"We need to look at the system in the same way Cadence and Ansys simulate transistors," Quantum Elements co-founder and CEO Izhar Medalsy told us earlier this year. On this month's paper, he said the work "shows the power of hybrid approaches to move us towards fault tolerant quantum computing."

What does this change for fault-tolerant design?

Matching a QPU's physical layout to the surface code's two-dimensional grid has been treated almost as a hard requirement. The USC and Quantum Elements result says it isn't.

"Implementing the surface code on other QPUs with different fixed connectivities is a problem of both fundamental interest and practical importance," the researchers wrote in Nature. QPU designers worried about frequency crowding, crosstalk, and thermal management don't have to surrender those wins just to fit a square grid.

IBM telegraphed the possibility five years ago. When Big Blue first picked heavy-hex as the topology for all its quantum devices, its engineers wrote that "the connectivity of other lattices, such as the square lattice, can be simulated on the heavy-hex lattice with constant overhead by introducing swap operations within a suitably chosen unit cell."

How did the team clear the routing penalty?

Heavy-hex trades uniform connectivity for reduced neighbor collisions. Fewer crosstalk headaches in the lithographic fab, more pain for any code that assumes each qubit reaches four neighbors on a square grid.

The answer came from Quantum Elements' Orbit tool, released in July via IBM's Qiskit Functions Catalog. Orbit layers in dynamical decoupling — pulses that protect idle qubits from noise — combined with SWAP-based embedding that ferries logical qubits across non-adjacent physical hardware.

The researchers also picked a depth-efficient variant of the surface code, cutting the sequential gate layers that otherwise leave qubits exposed during long waits. Step by step, the experiment ran the error-rate curve from above the threshold to below it.

What's the commercial angle?

Quantum Elements isn't building chips. It sells software. Its Constellation platform wraps AI agents around quantum simulators so customers can prototype algorithms before burning hours on real hardware — the same virtualization playbook that turned Cadence and Synopsys into billion-dollar EDA franchises.

Orbit is the first third-party tool with an IBM Qiskit storefront. That visibility matters as enterprise quantum teams weigh which software layer to standardize on through 2026.

For IBM, Heron stays competitive with Quantinuum, IonQ, and Rigetti even though none of those vendors lock their chip layouts to the surface code. Quantum Elements gave IBM something rarer than a benchmark: a working detour around its own architectural compromise.

Watch the depth budget. If depth-efficient codes keep cutting SWAP overhead on heavy-hex lattices, expect IBM's next Condor-class device to lean harder on the compatibility — and expect competitors to argue their own topologies were never constrained in the first place.

Original: ibm.com

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Rebecca Stone

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Correspondent covering technology and product news in Semiconductors, chip manufacturing, hardware, AI compute at Chip Dispatch.

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