Tesla SI6 Targets 80X HW4 Compute; Dojo D3 Drops Wafer-Scale SRAM

Tesla says its sixth-generation inference accelerator, SI6, will deliver 80 times the compute of today's HW4 chip and 144 GB of memory when it arrives in 2029–2030. The figure translates to an estimated 17,280–46,080 TOPS, or 17.28–46.08 POPS, though Tesla has not disclosed the chip's supported data formats. These are estimates, not confirmed specifications. For context, Nvidia's Rubin GPU offers 50 NVFP4 PFLOPS for inference and is shipping to customers today.

Tesla disclosed the roadmap alongside a rebranding. The company now calls its AI processors "Super Intelligence" accelerators, renaming them with SI monikers and retrofitting older chips. HW4 became AI4, then SI4. Elon Musk recently confirmed SpaceXAI would be renamed SpaceXSI for the same reason.

What does the roadmap confirm about process nodes?

The slide fixes process technologies for several generations. The current SI4, used in Tesla vehicles for Full Self-Driving, is fabricated by Samsung Foundry on a 7nm-class node with FCBGA packaging and presumably 16 GB of GDDR6. The alleged slide contains an error claiming 5nm, the original report notes. Tesla does not officially disclose SI4's absolute compute, memory, or power figures.

Musk once said HW4 is 3X–8X more powerful than HW3, which was officially rated at 72 TOPS. That puts SI4 at an estimated 216–576 TOPS. HW3 itself used Samsung 14nm and carried 8 GB of LPDDR4.

The SI5, nearing production, will be built on TSMC 3nm and Samsung 2nm-class processes. It adopts a multi-chip module design instead of monolithic silicon. Tesla expects 40X performance over HW4, which Musk attributed to an eightfold compute increase from denser nodes and more execution units plus a fivefold gain from silicon optimization. Estimated output is 8,640–23,040 TOPS. SI5 will carry 96 GB of memory, six times its predecessor, and consume 250W to 800W depending on application. Memory bandwidth will range from 768 GB/s to 1.536 GB/s depending on whether it uses GDDR6 or GDDR7.

Where will SI6 be built?

Tesla has signed a deal with Samsung Foundry to produce its sixth-generation inference accelerators through 2033. The slide confirms a 2nm-class process. Given the 2029–2030 timeframe and Samsung's updated foundry roadmap, the candidates are automotive-grade SF2A, performance-enhanced SF2P, or SF2Z with backside power delivery.

One omission stands out: the roadmap does not envision SI6 production at Intel's Terafab using the 14A process in the 2030s. SI6 keeps the MCM approach introduced with SI5, which lets Tesla leverage experience from that chip and hold packaging costs down. HBM adoption for inference accelerators remains unlikely with SI6, though many automakers are considering chiplet designs and HBM for next-generation system-in-packages.

Does Dojo D3 abandon wafer-scale integration?

Dojo D3 marks the return of Tesla's training accelerator after Musk cancelled the wafer-level Dojo project in August 2025 and said in August 2026 that SpaceX and xAI would use Nvidia hardware exclusively in terrestrial and extraterrestrial data centers. D3 differs sharply from its predecessors. Tesla describes a chiplet-based design combining 2.5D and 3D packaging with stacked HBM.

The first-generation Dojo D1 used a system-on-wafer architecture with distributed on-chip SRAM, interconnecting 25 processors with 11 GB of SRAM per wafer through wafer-scale packaging, offering roughly 10 TB/s of on-chip bandwidth. D1 was built on TSMC 7nm. The move to HBM signals that Tesla needs memory capacity for model parameters, activations, and intermediate data, which SRAM cannot supply economically.

The source analysis argues wafer-scale integration is now unlikely. Stacking HBM atop wafer-interconnected logic adds design complexity, cooling challenges, yield risk, and reliability concerns. Redundancy and process refinements can address these issues, but at a cost. Tesla says D3 will be optimized for "space, training, and scaling," a formulation that points to a conventional, scalable accelerator architecture. Extraterrestrial optimization likely means radiation hardening for select SKUs. D3's performance, memory capacity, process node, and schedule remain undisclosed.

The roadmap leaves two open questions for suppliers and rivals: whether Tesla commits its volume inference business solely to Samsung through 2033, and whether Dojo D3's chiplet redesign can compete with Nvidia's training hardware by the end of the decade.