TSMC taps GlobalFoundries for $2 billion silicon interposer deal
GlobalFoundries and TSMC have signed a $2 billion deal covering silicon interposers for CoWoS advanced packaging, pulling the US foundry into an AI accelerator supply chain dominated by Taiwan.
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GlobalFoundries and TSMC have signed a $2 billion agreement covering silicon interposers for CoWoS advanced packaging, a deal that pulls a United States foundry into a supply stream Taiwan has held alone.
CoWoS, short for Chip-on-Wafer-on-Substrate, is TSMC's family of 2.5D packaging flows. It carries the bulk of AI accelerator integration today.
The silicon interposer sits beneath stacked logic and high-bandwidth memory dies. As die counts climb toward eight and twelve per package, the interposer grows larger and yield losses accumulate. CoWoS has throttled shipments of leading AI accelerators since 2023.
GlobalFoundries brings an existing 300mm interposer capability, drawn from its work on the 22FDX and 12LP+ processes. The Malta, New York facility, which received federal CHIPS Act funding, will serve as the principal site. The company has shipped interposers for RF and photonics customers for years.
It has not, until now, served TSMC's high-volume CoWoS line.
What does the agreement actually cover?
Neither party has disclosed whether the $2 billion figure represents a multi-year purchase commitment, a capacity reservation, or a co-investment in equipment. Each reading points to a different commercial outcome, which is why the structure matters more than the headline number.
Both firms have confirmed that GlobalFoundries will qualify its 300mm interposer process against TSMC's CoWoS-S reference flow. Qualification timelines for advanced packaging typically stretch beyond a year, which places any meaningful volume contribution in 2026 at the earliest.
What does the qualification work involve?
CoWoS-S interposers reach roughly 100 millimeters per side for current-generation AI accelerators. The next generation, designed for 3nm and 2nm logic stacks, demands fine-pitch through-silicon-via alignment that GlobalFoundries has not publicly demonstrated at production scale. That learning curve at Malta functions as the deal's real risk.
The TSMC interposer line runs on 300mm wafers at process dimensions well above the leading-edge logic node. The transfer remains more manageable than a leading-edge logic technology transfer would be. Through-silicon-via density still poses work for engineers in upstate New York.
Why does the US site matter?
Geopolitics sit underneath the commercial logic. Washington has classified advanced packaging capacity as critical infrastructure under the CHIPS Act framework, and interposers now join lithography and high-bandwidth memory in that category. A $2 billion deal that moves a slice of the CoWoS flow onshore fits the policy intent, even if the largest pieces remain in Hsinchu and Kaohsiung.
GlobalFoundries leadership has framed advanced packaging as the next foundry battleground, though not at the expense of leading-edge logic. The company has spent the past two years reorganizing around RF, automotive, and photonics rather than chasing the leading node, which makes this CoWoS interposer work a noticeable departure.
What about competing packaging approaches?
Intel's EMIB flow uses embedded silicon bridges rather than full interposers. Other outsourced assembly providers have offered licensed TSMC CoWoS-S services outside Taiwan. GlobalFoundries joins a supplier list with established peers but lands as the first US-based foundry qualified to a TSMC-licensed 2.5D flow at production scale. That distinction registers mainly in Washington.
What changes for AI accelerator buyers?
Hyperscaler customers and accelerator vendors gain a second qualified source for interposers at a moment when Nvidia, AMD, and Broadcom have all reported packaging constraints. A second source reduces single-supplier risk for buyers uneasy with Taiwan concentration. It also tests whether a US-based foundry can compete on a process step TSMC has treated as proprietary.
Pricing terms remain undisclosed. Volume ramp timing remains undisclosed. The careful verdict for now is that the agreement exists, the figure is real, and the bottleneck in AI accelerator packaging has one more supplier attached to it.
Whether that supplier ships at volume by the second half of 2026 will determine whether the deal relieves a constraint or simply signs paperwork.
Source: Google News: TSMC
More from Nathan Brooks
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Senior reporter covering people, launches and day-to-day practice in Semiconductors, chip manufacturing, hardware, AI compute at Chip Dispatch.
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