TSMC plans 3nm semiconductor manufacturing at second Japan factory, investment to exceed USD 23 billion - ANI News

Chip Manufacturing

TSMC to Bring 3nm Production to Second Japan Fab, Investment Above $23 Billion

TSMC plans 3nm production at a second Japan fab with investment above USD 23 billion, extending its Japanese footprint beyond Kumamoto's specialty nodes.

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Nathan Brooks
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TSMC plans to manufacture 3nm chips at a second factory in Japan, with total investment in the project exceeding USD 23 billion, according to a report by ANI News. The figure, if confirmed by the company, would stand among the largest single-country manufacturing commitments TSMC has made outside Taiwan.

The number matters because it sets the scale. Twenty-three billion dollars buys a modern fab and the equipment to fill it, and the choice of 3nm as the target node signals intent to place leading-edge capacity, not mature-node capacity, on Japanese soil.

What does the second factory change?

TSMC already operates a subsidiary in Japan, JASM, which runs production at Kumamoto. That first site focuses on 12/16nm-class and 28nm-class processes — specialty technology aimed at automotive and industrial customers, not the leading edge. A second factory built for 3nm would move Japan's domestic supply chain a full technology generation closer to the frontier.

The distinction is commercial, not cosmetic. Automotive and image-sensor customers can live with 28nm. Smartphones, high-performance computing and AI accelerators cannot. If the reported plan proceeds, Japan would host process technology that today exists in volume only in Taiwan and, in earlier ramp stages, at TSMC's Arizona site.

How firm is the plan?

The report describes an intention, not a completed board decision with a groundbreaking date. TSMC has a record of phrasing its overseas expansions carefully, and the USD 23 billion figure should be read as the reported envelope for the project rather than a booked capital expenditure. Confirmed figures, when they arrive, tend to appear in the company's quarterly announcements with subsidy terms attached.

Japan's government has already shown willingness to pay for advanced domestic capacity, and Tokyo's subsidy programs have covered a meaningful share of foreign fabs built in the country. That support changes the arithmetic for any 3nm site, since leading-edge tooling costs more per wafer of capacity than anything TSMC has built in Japan to date.

Why Japan, and why now?

The geopolitical logic is straightforward. Concentrating leading-edge production in one location concentrates risk, and TSMC's customers — particularly American and Japanese buyers of AI silicon — have pressed for geographic spread. A 3nm line in Japan complements the Arizona ramp rather than competing with it, since each region carries its own customer base and its own subsidy structure.

For Japan, the appeal runs the other way. The country's device makers once led the world in lithography-adjacent equipment and still supply a large share of the tools a 3nm fab requires. Domestic leading-edge demand gives those suppliers a nearby anchor customer.

The comparison worth keeping: USD 23 billion is roughly the cost of two N7-generation fabs a decade ago. Inflation in fab construction and extreme-ultraviolet tooling has made each leading-edge site a national-scale bet, which is precisely why governments now co-fund them.

What comes next

Watch for three confirmations: a formal TSMC announcement with a construction timeline, a Japanese government subsidy figure, and a capacity target in wafers per month. Until those arrive, the USD 23 billion figure and the 3nm designation remain a reported plan — a serious one, given the source, but a plan. If TSMC confirms it, Japan becomes the second country after the United States with announced leading-edge TSMC production outside Taiwan, and the map of advanced silicon gets one node wider.

By Nathan Brooks

Source: Google News: TSMC

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Nathan Brooks

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Senior reporter covering people, launches and day-to-day practice in Semiconductors, chip manufacturing, hardware, AI compute at Chip Dispatch.

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