AMD's Zen 6 EPYC 'Venice' Beats Nvidia's Vera in First Tests

A dual-socket EPYC 9996 server running 1,024 threads scored 93% higher than the 768-thread 2P EPYC 9965 in SPEC CPU 2026's intrate throughput test — the headline number from Tom's Hardware's first deep dive into AMD's Zen 6 architecture, tested over several weeks on the new 'Venice' EPYC family.

Venice is the first shipping design on Zen 6, and Senior CPU Analyst Jake Roach tested two SP7 SKUs: the 256-core EPYC 9996 (512 threads per socket, 1,024 MB of L3, 600W TDP, 2.55/4.1 GHz base/boost) and the frequency-optimized 96-core EPYC 9686F (192 threads, 384 MB L3, 500W TDP, 3.4/5 GHz). AMD has positioned the 9686F as its answer to Nvidia's Vera CPU — and largely, it delivers.

What does the new architecture change?

Zen 6 is built on TSMC's N2P node, an optimized version of N2 that TSMC says delivers 18% higher speed at iso-power versus N3E, 36% lower power at iso-speed, and 15% higher density. AMD claims a 27% average IPC uplift over Zen 5 in enterprise, cloud and AI workloads — though that figure came from comparing fixed-frequency Zen 5 against Zen 6c with 16 cores, and applies to data center workloads specifically.

Inside the core, AMD split the integer schedulers (96 shared ALU/AGU plus 48 dedicated ALU entries, versus an 88/56 unified split on Zen 5), grew the physical register file from 240 to 352 entries, and expanded the op cache to 6.75K entries serving up to 18 micro-ops per cycle. The vector engine now natively supports half-precision AVX-512 FP16 instructions, and FP load bandwidth doubles: two 512-bit loads or four 256-bit loads per cycle.

The bigger story is CCD density. For the first time since Zen 3, AMD upgraded the compute dies: a standard Zen 6 CCD scales to 12 cores (up from 8), while Zen 6c packs 32 cores (up from 16). Zen 6c also doubles L3 per core from 2 MB to 4 MB, giving its CCD 128 MB of L3 — quadruple a Zen 5c CCD. Peak clocks rose from 5 GHz to 5.3 GHz on Zen 6, and from 3.7 GHz to 4.1 GHz on Zen 6c.

The single IOD of previous generations is now two, giving SP7 access to 16 memory channels per socket (8 per IOD), up to 12,800 MT/s with MRDIMMs, 8 TB of memory and 1.6 TB/s of bandwidth per socket. The trade-off: PCIe 6.0 lanes compared with the SP8 platform, which swaps memory channels (8 instead of 16) for lanes (128 PCIe 6.0 per socket).

How does Venice stack up against Vera?

In SPEC CPU 2026 intrate estimates, the 9686F finished 17% ahead of Vera; in fprate it leads by 40%. Both Zen 6 chips more than doubled the fprate scores of the Zen 5 touchpoints. In SPEC speed suites, the 9686F beats Vera by 21% in integer.

Memory tells a subtler story. AMD leads STREAM by 11–19% with the OpenMP 'true' binding policy, but Vera's monolithic mesh wins with the 'spread' policy. In Python — critical for agentic AI frameworks like LangGraph and CrewAI — the 9686F was 32% faster than Vera in PyBench and leads most PyPerformance tests. In Java SciMark it posted a 92% composite lead over Vera. In HPC, the 9686F ran more than twice as fast as Vera in CloverLeaf and nearly twice in FFTE. Blender gains reached 30–40% gen-on-gen, with the 9996 finishing the Barbershop render 35% faster than the 9965.

Vera still holds pockets: Octave, C-Ray, cold-cache Clickhouse performance and FFTs. Intel's Granite Rapids-AP 6980P, tested on a Supermicro SYS-222HA, was rarely competitive.

What about power and memory features?

Venice adds three management features. Unified Power Provisioning (UPP) cut provisioned power 15% in AMD's testing — 830W across 16 servers versus 706W across 18. Utilization Based Power Scaling (UBPS) aligns platform power with workload. FAST, the most interesting, splits one socket into two performance tiers: on a 96-core chip, 32 'premium' cores run at 3.65 GHz base and 5 GHz max while 64 'batch' cores run at 2 GHz base and 2.4 GHz max — effectively multiple commercial SKUs in a single socket.

Venice also introduces MEXT, the memory-expansion technology AMD acquired earlier this year. A Linux kernel module uses a transformer-based LLM to predict which pages a workload needs, offloading untouched pages to flash. AMD says it runs the software internally on 145 servers — expanding past 2,000 next year — and claims 95% application performance on just 50% of system DRAM for workloads like Synopsys PrimeTime, and 80% performance at 25% DRAM.

What comes next?

The enterprise SP8 socket arrives within months. Next year brings Venice-X with 3D V-Cache for HPC, the LPDDR5X-based Verano platform with replaceable SOCAMM2 DIMMs — AMD's take on Vera's approach — and the consumer Olympic Ridge launch, where boost clocks should climb higher. Intel's Diamond Rapids lands next year too, but the two tested SKUs already hand AMD a leading position among current data center CPUs, and the roadmap suggests the bar keeps rising.