Chiplet Designs Push Past 50 Million Pins and Into STCO

Modern AI-driven chip designs now exceed 50 million total pins and hundreds of thousands of die-to-die connections. That figure, cited by Siemens Digital Industries Software, explains why single-die design tools can no longer carry multi-die development. The industry answer is system-level technology co-optimization, or STCO. It is a method, not a product. And it comes with caveats that vendors do not always advertise.

STCO optimizes silicon, package, interposer and PCB together from the start, rather than layer by layer. Siemens claims this simultaneous view improves power, performance, area and cost, plus reliability and safety. The promise is fewer iterative design cycles. The unspoken condition is that every domain must live inside one tool chain for the promise to hold.

What does the digital twin actually contain?

The workflow begins with a full 3D digital twin of the entire device assembly. Engineers aggregate diverse design IP into one system model, which serves as the single authoritative source of connectivity. That model then drives the creation of interfaces and bump arrays for chiplets, bridges, interposers and substrates.

The aggregation step is where projects stumble. Manual processing is error-prone and lacks the repeatability hyperscale designs demand. Standard formats exist — IEEE 3Dblox, OCP CDX and JEDEC JEP30 — yet engineers still meet randomized data formats in practice. Robust revision control and consistent netlists are prerequisites, not extras, because later layout-versus-schematic checks, logical equivalency checking and multiphysics analysis all depend on them.

How do engineers manage the connection explosion?

Spreadsheets do not scale. Bit-by-bit definitions cannot handle the millions of bumps required by hybrid and direct bonding technologies. Designers are shifting to language-based design instead. Writing Verilog RTL with proper bus notation is significantly more efficient and less error-prone, according to Siemens.

Hierarchical design adds another layer of control. Designers disaggregate the system into building blocks and define topological pin regions using formulas, regular expressions and design attribute tokens. This enables rapid instantiation of silicon bridges and interposers, which carry signals between CPUs, GPUs and high-bandwidth memory stacks at low latency and low power.

Why does pathfinding come before sign-off?

Pathfinding explores integration scenarios against PPAC targets before commitments harden. Engineers manipulate all system blocks, including mechanical parts such as heat spreaders and stiffeners, in a single cockpit. Mechanical parts consume real estate and electrical clearances. Finding those conflicts early is cheaper than finding them late.

Predictive analysis makes or breaks the process, as the author puts it. Power delivery network planning uses "shift-left" analysis to catch DC-drop issues early, prioritizing problem detection over absolute sign-off accuracy. Thermal behavior matters even more. Vertical chiplet stacking blocks traditional heat-removal paths through the die's top and bottom, while die thinning raises lateral thermal resistance. Siemens says 3D-optimized EDA tools model thermal gradients and mechanical stress across the assembly so co-design choices do not create unmanageable reliability problems.

What changes in test and verification?

Die-level testing stays consistent with 2D processes. But 2.5D and 3D packages need die-to-die interconnect testing and stack-level verification. Hierarchical DFT principles extend to the stack level: pattern generation runs at a lower hierarchy, then retargets to the die-top and stack-level top, so automatic test pattern generation executes only once. Heat from testing one die can affect adjacent dies in a stack — a thermal coupling problem the DFT flow must model.

Formal sign-off has historically been a bottleneck for 3D ICs, especially with chiplets drawn from multiple process nodes and foundries. Package assembly design kits and integrated verification tools are closing that gap. The flow runs substrate and interposer design rule checks, then validates the complete assembly for electrical connectivity and physical alignment. Some 3D IC tools support exhaustive, automated verification against the golden netlist. Automated daisy-chain test vehicle creation ensures logical-to-physical continuity.

How is UCIe compliance reached?

Universal Chiplet Interconnect Express is now the de facto standard for logic-chiplet-to-logic-chiplet links. Compliance demands pre-route signal integrity pathfinding across substrate materials, layer stackups and trace dimensions. Standards-based analysis secures basic interoperability. IBIS-AMI models go further, predicting real-world performance with equalization and clock data recovery algorithms. AI-driven search, including Siemens' SHERSA-family SHERPA algorithm, explores the design space with the fewest simulations needed for compliance.

Siemens frames the payoff as compliance, thermal, manufacturing and testability readiness before physical implementation, cutting iteration cycles and accelerating time to production. Whether STCO delivers that acceleration at scale will show in the first hyperscale chiplet programs that run third-party and proprietary IP through this full flow without falling back on manual glue work.