Cognichip claims 10-day RTL turnaround, but the spec was already written

Cognichip claims its Artificial Chip Intelligence platform turned a 55-page microarchitecture specification into functionally verified RTL in 10 days with one engineer. The same task, the company says, would take a conventional front-end team about 20 weeks. The claim comes from an evaluation with an unnamed fabless customer. Cognichip disclosed neither the design's complexity nor the customer's identity. Those omissions matter.

Chief Product Officer Stelios Diamantidis told Tom's Hardware that ACI achieved over 90% UVM coverage in the exercise. The system generated SystemVerilog testbenches, ran simulations, found and corrected errors, and reached verification closure. It also integrated middleware and other components. That is front-end work only. Physical implementation, tape-out, manufacturing and silicon validation remain outside the platform.

What is actually on offer?

Cognichip launched ACI in September. The company describes it as proprietary AI models built for semiconductor engineering, trained on what it calls the industry's largest dataset in the field. Diamantidis put a number on it: "We have surpassed, I think, over ten million training samples in our datasets." Some samples were designed in-house. Others came from synthetic generation technology the company invented.

ACI Enterprise packages the models with agentic workflows, project memory and inference infrastructure. The pitch: engineers write specifications and make architectural decisions. The system generates RTL, verifies it, and optimizes for power, performance and area targets.

"We do not try to turn the designer into a verification engine; our system is self-verified, so we want the designer to design," Diamantidis said. He claims a self-learning flywheel keeps abstractions aligned, so changes in microarchitecture reflect automatically in RTL and vice versa.

The company reports more than 40 customer engagements, including projects at Renesas and SiTime. Designs span microcontrollers, encryption engines, networking processors, RISC-V CPUs and AI accelerators. Engagement depth was not quantified.

How good are the PPA predictions?

The core claim is prediction accuracy. Cognichip says its models predict certain PPA characteristics at the pre-route stage with roughly 10% error. The company validated this on 1,200 open-source designs. General-purpose models — Anthropic's Claude Opus and Google's Gemini — showed errors of 50% to 100% on the same metrics, according to Diamantidis.

The 10% figure carries a caveat. It applies to pre-route results, not post-route characteristics. Actual routing introduces parasitics that can shift timing and power. A design estimated at 1 GHz and 15 W might land at 800 MHz and 20 W after implementation. Diamantidis acknowledged the limit: "We do not have much physical information at all, right?"

"Today we do not do physical implementation. So, place and route […] is done outside of our system," he said. Place-and-route, clock-tree synthesis and signoff still require tools from Cadence, Synopsys and Siemens EDA.

Cognichip has not disclosed which foundry nodes its models support. Diamantidis framed early architectural decisions as node-agnostic, with node awareness needed only later in development. Accuracy variation across nodes went unaddressed.

SoC integration and third-party IP

ACI handles IP blocks and subsystems of millions of logic gates, the company says. It supports flat and hierarchical optimization and can decompose system-level constraints into per-block requirements. Whether Pareto-optimal blocks assemble into a Pareto-optimal SoC is a harder question, and the company offered architecture rather than evidence. "Yes, ACI can align and optimize individual blocks to global SoC and subsystem constraints," Diamantidis said.

Third-party IP works through interface specifications alone. "We ourselves do not ingest the guts of the IPs, nor do we try to train on any kind of data related to the IPs," he said. ACI Enterprise runs in firewalled data centers with multi-tenant isolation and SOC 2 Type II validation.

The open questions

Cognichip has not demonstrated autonomous development of a complete, physically validated chip. Its promise to eliminate front-end-to-back-end feedback loops rests entirely on prediction accuracy the company itself caps at 10% error, pre-route only. If physical implementation exposes problems, engineers return to ACI with feedback and revise — the file format for that feedback is unspecified.

For startups lacking engineering depth, automated RTL and verification may still lower the cost of custom silicon considerably. Until Cognichip publishes a tape-out with post-silicon numbers, its productivity claims remain estimates the company generated itself, on designs it chose not to describe.