CoWoS-L will remain the leading packaging technology for AI chips through 2028, according to an EE Times Asia report — a projection that extends the roadmap for TSMC's most advanced chip-on-wafer-on-substrate variant well beyond the current generation of AI accelerators now shipping in volume.

The designation matters commercially. CoWoS-L is the packaging family TSMC developed for the largest AI devices, pairing compute dies with high-bandwidth memory (HBM) stacks on silicon interposers with local silicon interconnect bridges — the so-called LSI bridges — that sit between the logic die and adjacent HBM stacks. It is the packaging platform behind the current class of flagship AI accelerators, and its continued leadership through 2028, as EE Times Asia reports, implies that the interposer-and-bridge architecture, not a wholesale replacement, will carry the next several generations of those products.

That timeline is a projection, not a confirmed capacity figure, and it should be read as such. EE Times Asia frames CoWoS-L's dominance as extending to 2028; the report does not, in the material available, attach specific wafer-per-month capacity numbers or revenue figures to that outlook. What the projection does establish is the expected competitive ordering within advanced packaging: CoWoS-L ahead of other variants and rival platforms for roughly the next four years.

The commercial logic behind that ordering is straightforward. AI accelerators keep growing in die area and memory bandwidth, and CoWoS-L's local-silicon-interconnect approach buys more bandwidth per package than the earlier CoWoS-S generation, which relies on a full silicon interposer alone. As long as accelerator vendors push larger compute die complexes and more HBM stacks per package, the packaging tier that supports the largest reticle-limit-busting assemblies tends to hold the highest-value position in the supply chain.

For buyers and silicon designers, the projection carries planning weight. A packaging platform that stays in the lead through 2028 means products designed into CoWoS-L now have a multi-generation supply runway, and companies qualifying alternative packaging suppliers face a moving target rather than a static incumbent. For TSMC, the projection reinforces the position of advanced packaging as a revenue pillar distinct from front-end wafer fabrication — one where the AI demand cycle concentrates value at the assembly stage as much as at the lithography stage.

The competitive context is thin in the available report, and it is worth keeping the claim within its bounds. EE Times Asia's headline positions CoWoS-L as the leading technology through 2028; it does not quantify how close challengers such as panel-level packaging, alternative bridge interconnect schemes, or other foundries' 2.5D offerings will come within that window. Analysts covering the packaging market have repeatedly flagged capacity, not architecture, as the binding constraint on AI chip shipments in recent cycles, and any leadership projection implicitly assumes supply keeps expanding to meet accelerator demand.

The forward read is this: if the projection holds, packaging technology selection for AI silicon through the end of the decade effectively converges on CoWoS-L-class integration, and competition shifts to capacity allocation, yield on larger packages, and cost per interconnect — the areas where the next wave of AI hardware margins will be decided.