Intel 18A Claims 18% Efficiency Gain as 18A-P Enters Risk Production

By Sophie Lindqvist

Intel 18A-P is in risk production, and Intel Foundry expects an additional 9% performance-per-watt improvement over Intel 18A.

Intel 18A with PowerVia claims about 18% better performance per watt than Intel 3. These are Intel’s own comparisons, and the forum account cites no independent benchmark.

What changes beyond transistor scaling?

At a Global Semiconductor Alliance European Executive Forum presentation, Intel Foundry stated: “Power delivery, connectivity, advanced packaging, and supply chain resilience are emerging as the primary constraints on AI scaling.”

For years, the industry concentrated on transistor scaling. Intel now describes system-level optimization across compute, memory, packaging and interconnects as the practical route to further gains.

The company traced a shift from the system-on-chip model dominant a decade ago toward a “system of chips” built from specialized dies, memory stacks and accelerators. Intel argues that chiplets improve modularity, scalability and innovation cycles while supplying the performance advanced AI workloads require.

Intel Foundry says it is responding on two fronts. One involves advanced process and packaging development for customer AI systems. The other applies AI and machine learning across technology development and factory operations to improve quality, accelerate yield learning and shorten product launches.

Intel identifies three workload trends:

• Agentic AI: Multistep reasoning produces less predictable demand than traditional computing. Autonomous agents raise requirements for power delivery and high-performance connectivity.
• Physical AI: Intelligence moves into edge devices and real-world systems. Scalable AI-enabled automation and modeling become necessary for cost-effective, high-yield manufacturing. According to Intel, the foundry industry increasingly treats agentic and physical AI as long-term growth drivers.
• Sovereign AI: National programs favor secure, resilient and geographically diverse manufacturing for business continuity and national security. Intel Foundry says its production capabilities across North America, Europe and Asia give customers flexibility over manufacturing locations. The account gives no capacity figures for those sites.

Can Intel 18A deliver its efficiency claims?

Intel 18A uses RibbonFET gate-all-around transistors. Intel says the architecture improves electrostatic control and supports scaling beyond traditional FinFET designs.

PowerVia is central to the power-delivery claim. It routes power through the wafer backside, separating power and signal paths to reduce resistance, voltage drop and delivery noise. High-density metal-insulator-metal capacitors add power integrity. Intel reports three supporting results:

• Up to 10% more cell utilization.
• A 4% improvement in ISO-power performance.
• Nano through-silicon vias approximately 500 times smaller than conventional TSVs.

Backside power adds manufacturing complexity. Intel says it maintains 32 nm lower-metal pitches on the frontside, allowing direct-print patterning instead of more expensive multi-patterning while preserving a cost structure it claims remains competitive. It presents Intel 18A and Intel 18A-P as delivering better performance per watt and more efficient power delivery.

Intel points readers to the Intel 18A family technical brief for the underlying performance-per-watt details. No wafer size, capital cost or unit-price model appears in the account.

UCIe supplies the chiplet link. The Universal Chiplet Interconnect Express standard targets high-bandwidth, low-latency communication between chiplets, which Intel says simplifies integration and supports scalable heterogeneous systems.

Advanced packaging combines those links with I/O dies, advanced logic, high-bandwidth memory, 2.5D integration and 3D integration. Intel Foundry supports the package with EMIB-T, Foveros and Foveros Direct.

EMIB-T places power-transfer capability directly in the bridge structure. Intel says this improves efficiency and reduces inductive power droop across multi-die AI systems. In many applications, it can also remove the need for a full silicon interposer and reduce package-material requirements.

Foveros Direct uses hybrid bonding for 3D integration, stacking leading-edge compute dies on optimized base dies so each function can use the process best suited to its requirements. Intel frames this choice as a balance among performance, power efficiency and total cost of ownership.

Does factory AI change production?

Intel says AI and machine learning already run throughout its leading-edge process development and manufacturing workflows. Figure 1 maps that deployment across the manufacturing flow.

In design technology co-optimization, machine learning helps engineers search advanced-node design spaces involving power, performance and area tradeoffs. The company says this identifies optimal solutions more efficiently.

The factory data is substantial by volume. Intel facilities collect nearly one billion manufacturing images each week and generate petabytes of data. Machine-learning systems detect defects, classify failure patterns, identify yield risks and improve design rules. For Intel 18A designs, the company says this analysis finds layout problems earlier, before designs reach production.

Intel also applies neural networks and ensemble decision trees to isolate root causes and accelerate defect resolution. Intel Foundry said: “The result is faster learning cycles and more predictable yield progression as new technologies ramp into production.”

Digital twins and predictive-maintenance systems monitor equipment continuously, identifying potential tool problems before they interrupt production and helping maintain the uptime required for semiconductor operations that run around the clock. Intel says this helps customers bring next-generation AI systems to market faster and more efficiently.

The account does not disclose defect-reduction rates, target yields, fab capacity, customer adoption, pricing or shipment volumes. Intel’s commercial test is therefore whether risk production at 18A-P converts the claimed efficiency into predictable yields and competitive package economics, not another set of roadmap targets.