Researchers at NYCU and TSMC Corporate Research have built top-gate transistors from monolayer MoS2 using a 0.42 nm aluminum oxide buffer. Nature Electronics reports an equivalent oxide thickness near one nanometer, maximum transconductance of 0.45 mS μm⁻¹ at 100 nm channels, and combined thin dielectric scaling with sustained carrier mobility in the same device.

What problem does the interface solve?

Monolayer MoS2 carries no dangling surface bonds. That property helps carriers travel cleanly through the channel. It also makes uniform dielectric deposition difficult. Standard oxide growth leaves gaps, forms defects, and introduces disorder at the boundary between the semiconductor and the overlying gate oxide, scattering electrons and weakening the electrostatic control that a thinner dielectric is supposed to deliver in the first place.

A balance has eluded two-dimensional transistor researchers for at least a decade, forcing them to choose between stronger gate control from a thinner dielectric and higher carrier mobility from a cleaner channel.

How was the buffer built?

The team deposited an ultrathin epitaxial aluminum film directly onto monolayer MoS2 grown by chemical vapor deposition. They then oxidized the aluminum in place to produce an aluminum oxide layer 0.42 nm thick. The researchers then deposited a high-κ hafnium oxide dielectric over the buffer. The interface performs two jobs. It smooths the surface for hafnium oxide deposition and shields carriers from dielectric disorder within the channel, the paper states.

Although it spans only a fraction of a nanometer, the engineered region carries functional responsibility for transistor behavior, an unusually demanding assignment for a layer that thin in any practical process.

What numbers did the devices deliver?

Top-gate transistors with roughly 100 nm channels produced:

• Equivalent oxide thickness near 1 nm
• Maximum transconductance of 0.45 mS μm⁻¹
• Low leakage current
• Minimal hysteresis

The authors flag a caveat. The result comes from a single material system and one device geometry. No wafer-level yield, no reliability data, no integration metrics have yet been published for the buffer stack.

How does this square with manufacturing?

The team used CVD-grown monolayer MoS2 rather than mechanically exfoliated flakes. That choice matters because exfoliation does not scale to 300 mm wafers. The publication, however, reports no wafer-scale data. Independent groups will need to replicate the result across alternative 2D channels and dielectric stacks before any foundry treats interface engineering as a road-ready process option rather than a research curiosity.

"For many years, efforts to improve atomically thin transistors have largely focused on discovering better semiconductor materials," said Professor Wen-Hao Chang, the corresponding author from NYCU. "Our research shows that the atomic interface between materials can be just as important. By engineering that boundary, we were able to reduce one of the fundamental trade-offs that has limited two-dimensional transistors for many years."

Why do interfaces matter at this scale?

As transistor features approach a few atomic layers in thickness, the regions separating materials begin to dominate device behavior. Those regions measure only a fraction of a nanometer. They decide how electrons traverse the boundary from one material to the next, and that crossing now sets the ceiling on transistor performance more than the bulk materials on either side.

"When transistor components become only a few atomic layers thick, the interface is no longer simply the boundary between materials, it becomes an active part of the device," said Professor Tsung-En Lee, the corresponding author. "Learning to engineer these interfaces with atomic precision opens new opportunities for designing future semiconductor devices that would be difficult to achieve by changing individual materials alone."

Does this challenge silicon?

The paper frames the result as a path toward low-power logic and advanced electronics beyond conventional silicon scaling. It does not name a process node. It does not forecast production timing. Commercial vendors, equipment suppliers, and rival research groups have not yet weighed in, leaving the commercial picture largely undefined at this stage and competitive claims absent from the publication.

Integration data, multi-wafer reproducibility, and compatibility with standard back-end-of-line thermal budgets will decide whether the 0.42 nm aluminum oxide buffer becomes a manufacturing tool or remains confined to laboratory demonstrations.