Samsung to use TSMC technology for Nvidia's next-generation memory chips, Seoul newspaper reports - TradingView

Memory & Storage

Samsung Turns to TSMC Process Technology for Nvidia's Next-Gen Memory

A Seoul daily reports Samsung will build Nvidia's next-generation memory chips using TSMC process technology, reshaping the AI memory supply race with SK Hynix.

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Tom Whitfield
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Samsung plans to manufacture Nvidia's next-generation memory chips using TSMC process technology rather than its own fabs, according to a report by a Seoul newspaper carried by TradingView. The claim, if confirmed, would mark a notable shift in how high-bandwidth memory for AI accelerators reaches the market.

The report did not specify which memory product, process node, or production volume is involved. It also did not state when Samsung intends to begin output. Chip Dispatch could not independently verify the details, and neither Samsung, TSMC, nor Nvidia has commented publicly on the report.

What does the report actually say?

At its core, the story describes a division of labor. Samsung, the world's largest memory maker, would supply the memory devices themselves. TSMC, the world's largest contract chipmaker, would contribute the process technology on which key parts of those devices are fabricated.

That arrangement matters because Samsung has spent years trying to win AI-memory orders with chips made entirely in-house. A decision to lean on a rival's manufacturing for a flagship customer would signal that Samsung's own process does not yet meet Nvidia's requirements for this generation of product.

The takeaway is simple: Samsung keeps the customer, but TSMC keeps the most advanced wafer work.

Why would memory need leading-edge logic lines?

Modern AI memory is not a standalone part. High-bandwidth packages stack memory dies on top of, or beside, a logic die that routes data between the memory stack and the GPU. That logic die is fabricated on a foundry process, and its quality directly limits how fast the memory feeds the accelerator.

For several product generations, memory makers have bought these base dies from external foundries. If the Seoul report is accurate, Samsung would extend that pattern to Nvidia's next generation, placing the interface logic on TSMC silicon while retaining the memory stacks it builds itself.

In plain terms, the report suggests the brain of the memory package would come from TSMC, while Samsung supplies the storage layers.

What does this mean for the competitive picture?

For TSMC, the reported deal would deepen its grip on the AI supply chain, extending beyond GPUs into the memory that feeds them. For Samsung, it would preserve a major Nvidia relationship that might otherwise have gone entirely to SK Hynix, the current leader in AI memory supply.

SK Hynix already supplies the majority of high-bandwidth memory for Nvidia's accelerators and sources its logic dies externally. A Samsung-TSMC pairing would mirror that structure, giving Nvidia a second qualified supplier without forcing it to accept a weaker process.

Samsung's own foundry business would take the reputational hit, since the deal implies its leading-edge nodes still trail TSMC's for this class of work. The company has invested heavily to close that gap, and management has repeatedly framed foundry credibility as central to its earnings recovery.

The commercial logic, if the report holds, is that keeping the customer now outranks defending the fab.

What happens next?

The claim rests on a single newspaper report, without volumes, dates, or named products. Confirmation is likely to come only when Samsung, Nvidia, or TSMC announces qualified supply for the next accelerator generation, or when supply-chain disclosures reveal the sourcing of the logic dies. Until then, the report stands as a signal that competition in AI memory now turns as much on foundry partnerships as on memory cells.

-- Tom Whitfield

Source: Google News: TSMC

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Tom Whitfield

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Staff writer covering companies, deals and strategy in Semiconductors, chip manufacturing, hardware, AI compute at Chip Dispatch.

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