TSMC weighs 20% CoWoS price rise as AI packaging tightens

By Tom Whitfield

TSMC is considering a price increase of as much as 20% for CoWoS advanced packaging, according to TrendForce, which cited supply-chain sources and local media. The company has not confirmed the report.

What would a 20% CoWoS increase mean?

CoWoS, or Chip on Wafer on Substrate, combines logic dies and high-bandwidth memory (HBM) stacks in a single package. The arrangement gives AI accelerators the bandwidth required for demanding workloads. As chip designers add more compute and memory, however, each package becomes harder to build, and CoWoS already ranks among the tightest links in the AI supply chain.

If TSMC implements the increase, it would add cost at one of AI computing’s scarcest production steps. The source did not specify an implementation date, contract terms or which customers would face the increase. For buyers, the 20% figure remains a reported possibility rather than a confirmed price schedule.

How much has demand changed?

A September report said TSMC’s projected semiconductor-equipment requirements had almost doubled in six months as the company expanded production to meet AI demand. By July, expected equipment needs had reached 1.9 times the original estimate.

In that report, Cliff Hou, TSMC’s deputy co-COO, said: "Compared with the pattern 30 years ago, we have never seen the demand increase that much, that frequency of changes." The 1.9-times figure measures expected requirements rather than installed tools, leaving a material gap between planning and usable capacity.

Why do Blackwell and Rubin matter?

NVIDIA’s Blackwell architecture pairs two large GPU dies with eight HBM3E stacks within the package. The upcoming Rubin and Rubin Ultra architectures are expected to push integration further, placing more pressure on packaging and the supply chain that supports it.

Testing has become another bottleneck. Blackwell reportedly takes three to four times longer to test than NVIDIA’s previous-generation Hopper, while Rubin could require as much as seven times longer. Longer test cycles keep equipment occupied for longer, making it harder to raise output as demand grows.

GPUs do not have exclusive access to advanced packaging. Server CPUs and custom ASICs also need the process, so they compete with AI accelerators for the same constrained capacity. Packaging and test, rather than chip design alone, will set the pace of AI supply.

Can tools arrive fast enough?

Equipment lead times have reportedly stretched from three to six months to as long as eight months. Such delays make new capacity less responsive to sudden demand changes because tools must arrive before they can support packaging and test output.

TSMC reportedly placed this year’s equipment orders at existing prices rather than negotiating discounts or extra features. That departs from its customary use of purchasing scale to secure better terms.

Getting the tools on time now appears to matter more than getting them cheaply. New capacity helps only after scarce tools arrive, and those tools now take as long as eight months.

Can outside supply ease the constraint?

GlobalFoundries agreed earlier this month to produce silicon interposers for TSMC’s CoWoS in the United States. The five-year contract is worth $2 billion, and production is expected to ramp in the first half of 2028. The agreement broadens TSMC’s packaging supply chain, but interposers represent only one part of the packaging flow.

The contract will add U.S. interposer supply, yet its 2028 ramp leaves near-term shortages in other packaging steps unresolved. Interposer capacity can support the package process without eliminating the wider bottleneck.

What do price and capacity forecasts imply?\n

TSMC is also reportedly considering broader price increases for 2027. Wafer prices on advanced process technologies could rise by 5% to 10%, with customers using 2nm and 3nm-class nodes facing the steepest increases. Customers seeking capacity beyond their original allocations may also pay additional premiums, which could push some costs up by as much as 25%.

The possible 20% CoWoS increase would sit alongside these reported wafer-price plans. If both moves materialize, the report expects AI hardware costs to climb further, with some of that increase inevitably passed down the supply chain.

Industry estimates cited by TrendForce put TSMC’s monthly wafer capacity above 106,000 wafers in 2026, with a target of 227,000 in 2027. The expansion is intended to keep pace with demand for increasingly complex AI processors. These estimates describe wafer capacity rather than a CoWoS package-volume target, so they should not be read as a measure of packaging output.

More wafer capacity also cannot, by itself, remove assembly or testing constraints. Through 2027, the decisive variables will be whether CoWoS output and tool deliveries rise fast enough to absorb longer test cycles, and whether the reported package and wafer increases reach customer contracts.