TU Wien researchers have identified a 0.14-nanometer atomic gap that forms between 2D semiconductor materials and adjacent insulating layers, a separation they say imposes a fundamental limit on chip miniaturization.

The group, led by Professors Mahdi Pourfath and Tibor Grasser at TU Wien's Institute for Microelectronics, published the work in Science on May 9, 2026 (DOI: 10.1126/science.aeb2271). The team modeled how ultrathin 2D layers such as graphene and molybdenum disulfide bond to oxide insulators used in transistor gate stacks.

In most combinations, the two surfaces bind through van der Waals forces. That attraction proves too weak to seat the insulator flush against the active layer. A consistent gap remains, the authors reported. At 0.14 nanometers, the gap is thinner than a single sulfur atom. A SARS-CoV-2 virus particle measures roughly 700 times larger by diameter.

Why does the gap break device scaling?

The separation degrades the capacitive coupling that controls current through the gate. Without adequate coupling, the transistor cannot switch efficiently. Intrinsic channel mobility cannot rescue the device once the interface is poor.

Grasser called the limitation structural rather than material. "In many combinations of 2D materials and insulating layers, the bonding between them is relatively weak," he said. The layers are held together "only by so-called van der Waals forces," he added, and "no matter how good the intrinsic properties of the materials may be, the gap can become the limiting factor."

Advanced silicon gate stacks have already pushed effective oxide thickness below one nanometer, and the TU Wien result implies 2D channels face a comparable barrier unless the interface itself is redesigned.

What did prior research overlook?

Most published studies isolated 2D layers and measured carrier mobility or band gap in vacuum. Few tested realistic device stacks that include the dielectric a transistor requires.

Pourfath drew the line. "A 2D material alone does not make an electronic device," he said. "We also need an insulating layer, usually an oxide. And this is where things become more complicated from a materials science perspective."

Public roadmaps for sub-1 nanometer equivalent nodes list 2D materials as channel candidates, and the paper warns those plans may stall if channel and insulator engineering remain separate exercises.

What are "zipper materials," and how do they close the gap?

The team proposes a category it calls zipper materials. In those stacks, the semiconductor and the insulator form direct covalent bonds across the interface. The gap closes. Coupling recovers the level aggressive scaling demands.

Pourfath stressed co-design at the outset. "If the semiconductor industry wants to succeed with 2D materials, the active layer and the insulating layer must be designed together from the very beginning," he said.

Grasser framed the financial exposure plainly. "There is a risk of investing billions in an approach that simply cannot succeed for fundamental physical reasons," he said.

What changes for foundries and equipment suppliers?

The Science paper includes a screening framework. Pourfath and Grasser rank material pairings by interface capacitance ceiling. Pairs that clear the threshold stay in the running. Pairs that do not should exit the pipeline before fab capital is committed.

The study names no specific tools or wafer sizes. It targets the layer physics that determines whether sub-1 nanometer channel architectures remain viable at all, leaving roadmap committees to decide whether to adopt joint channel-and-dielectric engineering or continue treating the stack as two unrelated problems.