UC Riverside Team Quantifies HBM4 Controller Split Between Host and Base Die

HBM4 lets designers build memory controller logic into the base die of the memory stack itself, and a November 2026 paper from the University of California, Riverside now offers the first systematic quantitative study of how far that shift should go. Tharunya Yogananda and Wantong Li published the work, titled "Beyond Host-Side Control: HBM Controller Partitioning Across Host and HBM Base Die," as arXiv:2611.10930 under a Creative Commons Attribution 4.0 license.

The premise is concrete. Recent generations of high bandwidth memory, including HBM4, allow the base die of the memory stack to be manufactured on a logic process rather than a conventional DRAM process. That logic process can accommodate more complex controller functions placed next to the DRAM itself. The question the paper addresses is which functions belong there and which should stay with the host.

What does the study actually measure?

The authors divide the HBM controller into its main functional blocks and evaluate four distinct placements along a spectrum. The paper's abstract, quoted by Semiconductor Engineering, describes the design space plainly:

"We divide the controller into its main functions and evaluate four placements, from a complete host controller to a complete base die controller, with intermediate placements that move maintenance or scheduling to the base die."

The four options therefore span two extremes and two mixed configurations:

• A complete host-side controller, the traditional arrangement used in earlier HBM generations
• A complete base die controller, with all control logic moved into the memory stack
• An intermediate placement that moves maintenance functions to the base die
• An intermediate placement that moves scheduling functions to the base die

The physical setting for all four configurations is a silicon interposer, the layer on which the host device and the HBM stack sit side by side. That detail matters. Moving controller logic closer to the DRAM shortens the path over which control signals travel, and the interposer is where the partition boundary is drawn.

Why does HBM4 change the question?

The enabling fact is process technology, and the paper attributes the opportunity directly to it. Earlier HBM base dies were limited in what logic they could carry, so the controller resided on the host side almost by default. HBM4's logic-capable base die process removes that constraint. Once the base die can host complex logic, the placement of each controller function becomes an engineering choice rather than a forced decision.

The authors frame their contribution as a first. They present the work as the first systematic quantitative study of function-level controller placement between the host and the HBM4 base die. The claim is narrow but meaningful. Prior discussions of base die intelligence existed in industry roadmaps; a function-by-function quantitative comparison across four placements had not, according to the paper, been published.

What the paper does not say

The abstract excerpt available through Semiconductor Engineering does not report specific performance numbers, latency figures, power measurements, or area costs for any of the four placements. The published excerpt defines the design space and the methodology, not the results. Any claim about which placement wins, and by how much, requires the full paper. Readers evaluating the work for design decisions should treat the four-way comparison as the study's framework and consult the complete text on arXiv for the quantitative outcomes.

The excerpt also does not name a target application, such as AI accelerators or data center GPUs, even though HBM demand is dominated by those markets. Nor does it state which logic process the analysis assumes for the base die. Both omissions leave room for follow-up work and for vendor-specific answers that depend on process choice.

Who did the work and where to find it

The paper carries two authors, both from the University of California, Riverside: Tharunya Yogananda and Wantong Li. The full text is available at arXiv:2611.10930, dated November 2026, under a Creative Commons Attribution 4.0 license that permits redistribution. Semiconductor Engineering surfaced the paper through its research tracking in the same month.

What comes next

The study arrives as HBM4 moves from specification toward volume deployment, and its function-level framework gives memory and accelerator designers a structured way to decide where maintenance and scheduling logic should live; the competitive outcome, and the adoption of any single placement point, will show in the base die architectures that memory vendors disclose as HBM4 products reach production.