AMD’s 256-core Venice CPU challenges purpose-built agentic AI claims

By Grace Kim

AMD is now launching the Zen 6 EPYC 9006 family with a 256-core, 512-thread processor and two additional CPU ranges planned for release next year. AMD’s chief Zen architect and a corporate vice president rejected rival claims that the latest data center CPUs were purpose-built for agentic AI.

Madhu Rangarajan, AMD’s corporate vice president, said: “We think that the EPYC 9006 CPU is the best CPU for the agentic era, and spoiler alert, we didn’t magically know four years ago that agentic was going to be a thing.” He said AMD did not purpose-build “something for agentic.”

AMD does not classify Venice as a dedicated agentic CPU. The company instead positions general-purpose Zen 6 as silicon for agentic workflows. Rangarajan called those workflows “a diverse set of tasks” requiring compute across a full portfolio.

Mike Clark, AMD’s chief Zen architect, said: “I’m not going to mislead and act like I knew agentic computing was coming, or we knew it.” He added that AMD “did strongly believe that the CPU would always have a place in the software ecosystem of AI.” Clark said the company can now deploy that foundation for agentic compute workloads.

Nvidia has called its Vera CPU “purpose-built” for agentic AI. Arm says its AGI CPU was “designed for the demands of agentic AI.” AMD views those messages as a direct challenge to its continued data-center rise, which it links to agentic demand.

AMD’s timing defense rests on multi-year CPU development cycles. The report places the CPU-centered agentic frenzy around March. The company argues that this left too little time to design a new general-purpose data center CPU around the trend from the start. Rangarajan’s four-year reference places Zen 6 development well before that shift.

What changes with Venice?

Tom’s Hardware CPU analyst Jake Roach completed early testing of two AMD Venice processors, with results that favored differentiated CPUs rather than establishing one universal agentic winner.

• EPYC 9996: a dense processor with 256 cores and 512 threads, delivering peak throughput in Tom’s Hardware testing.
• EPYC 9686F: a frequency-optimized processor that went toe-to-toe with Vera in the AI host-node role.

AMD plans two additional ranges for next year:

• Venice-X: targets high-performance computing and adds a 3D-stack cache.
• Verano: goes directly after Vera as an AI host node and uses an LPDDR5X memory system.

Tom’s Hardware’s separate Vera testing also found strong performance vectors for agentic workloads. AMD uses that result to argue against what it describes as Nvidia’s and Arm’s single-SKU approach. Its argument is that agentic systems need several CPU configurations, rather than one part optimized for every task.

Which CPUs fit agentic workloads?

Agentic AI still has no fixed workload profile. The report says its CPU and memory demands have become clearer since the beginning of the year, but still depend on what each agent does and how many agents run concurrently. Several sandboxed agents in a data center raise that concurrency.

A coding agent generally calls more CPU-intensive tools than a web-browsing agent. An agent that queries a database can require stronger memory performance. The report also says some performance vectors cannot be addressed through SKU segmentation alone. It cites strong memory performance as an example.

At the most basic level, an agentic loop lets a large language model understand functions and pass arguments to those functions for execution, potentially spanning work defined in languages such as Python and Rust. That breadth supports AMD’s portfolio argument and Clark’s view of the CPU’s durable role in AI software.

AMD’s commercial pitch is breadth across throughput, frequency, host-node and forthcoming high-performance computing parts. Nvidia and Arm continue to attach agentic positioning to their latest CPUs. Neither the launch information nor the tests cited here disclosed pricing, shipment volumes or production capacity.

The next competitive checkpoint is next year’s Venice-X and Verano launches, particularly whether their cache and LPDDR5X designs can turn AMD’s workload-breadth argument into data-center share against Vera and Arm’s agentic positioning.