Cognichip Claims AI Compressed 20 Weeks of Chip Design Into 10 Days

Cognichip says its AI platform completed roughly 20 weeks of chip front-end work in 10 days with a single engineer. The claim comes from a test with an unnamed leading fabless chip company. The startup's Artificial Chip Intelligence (ACI) platform took the customer's existing 55-page microarchitecture specification and produced verified RTL, the company told Tom's Hardware.

The result needs qualification. ACI generated RTL from scratch, wrote SystemVerilog testbenches, ran simulations, fixed the errors it found and reached functional verification closure with over 90% UVM coverage. Cognichip says a conventional front-end team would need about 20 weeks for the same job. The customer supplied a detailed specification, so ACI did not start from a blank sheet, and Cognichip has not disclosed the design's complexity.

What did the test actually cover?

Only front-end engineering. Chief Product Officer Stelios Diamantidis drew the boundary plainly. "Today we do not do physical implementation," he said. Floorplanning, place and route, clock-tree synthesis and signoff still run on conventional tools from Cadence, Synopsys and Siemens EDA. The speed-up therefore applies to specification-to-verified-RTL work, not the full design flow.

Cognichip launched ACI in September. The product line, sold as ACI Enterprise, includes agentic workflows, project memory and inference computing. The company says the system can:

• Analyze specifications and explore microarchitecture options
• Generate and verify RTL
• Optimize designs for power, performance and area (PPA)
• Propagate microarchitecture changes automatically into the RTL, and vice versa

Diamantidis said its datasets now hold more than 10 million training samples, either designed in-house or generated synthetically.

How accurate are the PPA predictions?

Cognichip's pitch is catching PPA problems before RTL reaches physical design teams. The company says its models predict certain PPA characteristics within about 10% of conventional EDA results at the pre-route stage. On 1,200 open-source designs, it says general-purpose AI models were off by 50% to 100%.

Those figures carry caveats. They are pre-route, so routing parasitics can still change final timing and power. Cognichip has not said which foundry nodes it supports.

Who is using it?

Cognichip says it has run more than 40 customer engagements, including projects at Renesas and SiTime. The work spans microcontrollers, encryption engines, networking processors, RISC-V CPUs and AI accelerators.

The company raised $60 million in April. Seligman Ventures led the round, with Mayfield, Lux Capital and Intel CEO Lip-Bu Tan, who joined its board. At the time, Cognichip said it could cut chip design effort by up to 50% but named no customers or chips.

The company is not alone in applying AI to slow stages of the flow. Samsung recently said it cut an 18-hour chip simulation to 17 seconds on Nvidia GPUs.

The comparison is instructive. Samsung attacked one bottleneck, simulation runtime, with raw GPU compute. Cognichip targets the front-end loop of specification, RTL generation and verification, where engineering headcount and iteration time dominate cost.

What happens next?

Cognichip's claim rests on one disclosed test with an unnamed customer and an undisclosed design complexity. Independent verification is absent, and the 10-day figure excludes physical implementation entirely. If further customer engagements replicate the result across node types and design sizes, the pressure on front-end staffing models and on incumbent EDA vendors' pricing will be measurable rather than rhetorical.